mirror of
git://projects.qi-hardware.com/nn-usb-fpga.git
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113 lines
2.7 KiB
Verilog
113 lines
2.7 KiB
Verilog
//----------------------------------------------------------------------------
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// Wishbone DDR Controller
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//
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// (c) Joerg Bornschein (<jb@capsec.org>)
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//----------------------------------------------------------------------------
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`include "ddr_include.v"
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module ddr_rpath
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(
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input clk,
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input reset,
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// sample activate
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input sample,
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// RDATA async fifo
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input rfifo_clk,
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output rfifo_empty,
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output [`RFIFO_RNG] rfifo_dout,
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input rfifo_next,
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// DDR
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input [ `DQ_RNG] ddr_dq,
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input [`DQS_RNG] ddr_dqs
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);
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//----------------------------------------------------------------------------
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// RDATA async. fifo
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//----------------------------------------------------------------------------
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wire [`RFIFO_RNG] rfifo_din;
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wire rfifo_wr;
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wire rfifo_full;
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async_fifo #(
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.DATA_WIDTH( `RFIFO_WIDTH ),
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.ADDRESS_WIDTH( 4 )
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) rfifo (
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.Data_out( rfifo_dout ),
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.Empty_out( rfifo_empty ),
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.ReadEn_in( rfifo_next ),
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.RClk( rfifo_clk ),
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//
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.Data_in( rfifo_din ),
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.WriteEn_in( rfifo_wr ),
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.Full_out( rfifo_full ),
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.WClk( ~clk ),
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.Clear_in( reset )
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);
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//----------------------------------------------------------------------------
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// Clean up incoming 'sample' signal and generate sample_dq
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//----------------------------------------------------------------------------
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// anti-meta-state
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//reg sample180;
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//always @(negedge clk) sample180 <= sample;
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wire sample180 = sample;
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reg sample_dq; // authoritive sample flag (after cleanup)
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reg sample_dq_delayed; // write to rfifo?
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reg [3:0] sample_count; // make sure sample_dq is up exactly
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// BURSTLENGTH/2 cycles
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always @(posedge clk or posedge reset)
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begin
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if (reset) begin
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sample_dq <= 0;
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sample_dq_delayed <= 0;
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sample_count <= 0;
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end else begin
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sample_dq_delayed <= sample_dq;
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if (sample_count == 0) begin
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if (sample180) begin
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sample_dq <= 1;
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sample_count <= 1;
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end
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end else if (sample_count == 4) begin
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sample_dq <= 0;
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sample_count <= 0;
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end else
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sample_count <= sample_count + 1;
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end
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end
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//----------------------------------------------------------------------------
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// Sampe DQ and fill RFIFO
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//----------------------------------------------------------------------------
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reg [15:0] ddr_dq_low, ddr_dq_high;
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always @(negedge clk )
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begin
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if (reset)
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ddr_dq_low <= 'b0;
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else
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ddr_dq_low <= ddr_dq;
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end
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always @(posedge clk)
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begin
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if (reset)
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ddr_dq_high <= 'b0;
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else
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ddr_dq_high <= ddr_dq;
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end
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assign rfifo_wr = sample_dq_delayed;
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assign rfifo_din = { ddr_dq_high, ddr_dq_low };
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endmodule
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