82 lines
3.5 KiB
C
82 lines
3.5 KiB
C
/* ADC Peripheral.h
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Copyright (C) 2010 Carlos Camargo cicamargoba@unal.edu.co
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Andres Calderon andres.calderon@emqbit.com
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
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#ifndef __adc_peripheral_h__
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#define __adc_peripheral_h__
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#include "jz47xx_mmap.h"
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#include "jz47xx_gpio.h"
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#define ADC_CMD_NONE 0x00 /* Nothing to do */
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#define ADC_CMD_SET_SPI_CLKDIV 0x00 /* Set clock divider for ADC sclk */
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#define ADC_CMD_SET_BUFFER_SIZE 0x00 /* Set clock divider for ADC sclk */
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#define ADC_CMD_SET_CHANNEL0 0x30 /* Set channel 0 */
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#define ADC_CMD_READ_CHANNEL0 0x20 /* Read channel 0 */
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#define ADC_CMD_SET_CHANNEL1 0x31 /* Set channel 1 */
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#define ADC_CMD_READ_CHANNEL1 0x21 /* Read channel 1 */
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#define ADC_CMD_SET_CHANNEL2 0x32 /* Set channel 2 */
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#define ADC_CMD_READ_CHANNEL2 0x22 /* Read channel 2 */
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#define ADC_CMD_SET_CHANNEL3 0x33 /* Set channel 3 */
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#define ADC_CMD_READ_CHANNEL3 0x23 /* Read channel 3 */
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#define ADC_CMD_SET_CHANNEL4 0x34 /* Set channel 4 */
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#define ADC_CMD_READ_CHANNEL4 0x24 /* Read channel 4 */
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#define ADC_CMD_SET_CHANNEL5 0x35 /* Set channel 5 */
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#define ADC_CMD_READ_CHANNEL5 0x25 /* Read channel 5 */
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#define ADC_CMD_SET_CHANNEL6 0x36 /* Set channel 6 */
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#define ADC_CMD_READ_CHANNEL6 0x26 /* Read channel 6 */
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#define ADC_CMD_SET_CHANNEL7 0x37 /* Set channel 7 */
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#define ADC_CMD_READ_CHANNEL7 0x27 /* Read channel 8 */
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#define ADC_CMD_SET_POWER_DOWN 0X38 /* Set ADC power down mode (1uA) */
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#define ADC_CMD_SET_FAST_CONV 0X39 /* Initialize ADC Fast Convertion(<10us)*/
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#define ADC_CMD_SET_LOW_CONV 0X3A /* Initialize ADC Slow Convertion(<40us)*/
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#define ADC_CMD_SET_AUTOSELFT_1 0x3B /* Set Autoselft ADC {(Vref+)-(Vref-)}/2*/
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#define ADC_CMD_READ_AUTOSELFT_1 0x2B /* Read Autoselft ADC 1 (0x0200) */
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#define ADC_CMD_SET_AUTOSELFT_2 0x3C /* Set Autoselft ADC (Vref-) */
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#define ADC_CMD_READ_AUTOSELFT_2 0x2C /* Read Autoselft ADC 2 (0x0000) */
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#define ADC_CMD_SET_AUTOSELFT_3 0x3D /* Set Autoselft ADC (Vref+) */
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#define ADC_CMD_READ_AUTOSELFT_3 0x2D /* Read Autoselft ADC 3 (0x03FF) */
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#define ADC_SPI_CLKDIV_MIN 0x08 /* 50/(2*9) -> 2.78MHz (MAX=2.8MHz) */
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#define ADC_SPI_CLKDIV_MAX 0xFF /* 50/(2*256) -> 97.65KHz */
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#define ADC_MAX_BUFFER 0x3FE/* 1022 reads/commands */
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#define CS2_PORT JZ_GPIO_PORT_B
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#define CS2_PIN 26
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typedef unsigned char uchar;
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JZ_REG *jz_adc_init();
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#endif
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