64 lines
4.3 KiB
Systemverilog
64 lines
4.3 KiB
Systemverilog
/****************************************************************************************
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*
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* Disclaimer This software code and all associated documentation, comments or other
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* of Warranty: information (collectively "Software") is provided "AS IS" without
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* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGES. Because some jurisdictions prohibit the exclusion or
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* limitation of liability for consequential or incidental damages, the
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* above limitation may not apply to you.
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*
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* Copyright 2003 Micron Technology, Inc. All rights reserved.
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*
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****************************************************************************************/
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// Timing parameters based on Speed Grade
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// SYMBOL UNITS DESCRIPTION
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// ------ ----- -----------
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// `ifdef sg6T // Timing Parameters for -6T (CL = 2.5)
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parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
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parameter tDQSQ = 0.45; // tDQSS ns DQS-DQ skew, DQS to last DQ valid, per group, per access
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parameter tMRD = 12.0; // tMRD ns Load Mode Register command cycle time
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parameter tRAP = 15.0; // tRAP ns ACTIVE to READ with Auto precharge command
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parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
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parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
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parameter tRFC = 120.0; // tRFC ns Refresh to Refresh Command interval time
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parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
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parameter tRP = 15.0; // tRP ns Precharge command period
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parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
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parameter tWR = 15.0; // tWR ns Write recovery time
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// Size Parameters based on Part Width
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//`else `define x16
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parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
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parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
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parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
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parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
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parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
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parameter full_mem_bits = 2+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
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parameter part_mem_bits = 14; // Set this parameter to control how many unique addresses are used
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parameter no_halt = 0; // If set to 1, the model won't halt on command sequence/major errors
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parameter Debug = 1; // Turn on debug message
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