65 lines
3.3 KiB
Verilog
65 lines
3.3 KiB
Verilog
///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2005 Xilinx, Inc.
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// This design is confidential and proprietary of Xilinx, All Rights Reserved.
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : $Name: mig_v1_73_b0 $
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// \ \ Application : MIG
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// / / Filename : mem_interface_top_parameters_0.v
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// /___/ /\ Date Last Modified : $Date: 2007/06/06 05:44:42 $
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// \ \ / \ Date Created : Mon May 2 2005
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// \___\/\___\
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// Device : Spartan-3/3E/3A
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// Design Name : DDR1 SDRAM
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// Purpose : This module has the parameters used in the design.
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///////////////////////////////////////////////////////////////////////////////
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`define data_width 16
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`define data_strobe_width 2
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`define data_mask_width 2
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`define clk_width 1
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`define fifo_16 1
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`define ReadEnable 1
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`define memory_width 8
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`define DatabitsPerReadClock 8
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`define DatabitsPerMask 8
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`define no_of_cs 1
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`define data_mask 1
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`define mask_disable 0
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`define RESET 0
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`define cke_width 1
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`define registered 0
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`define col_ap_width 11
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`define write_pipe_itr 1
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`define write_pipeline 4
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`define top_bottom 0
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`define left_right 1
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`define row_address 13
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`define column_address 10
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`define bank_address 2
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`define spartan3e 1
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`define burst_length 3'b001
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`define burst_type 1'b0
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`define cas_latency_value 3'b110
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`define Operating_mode 5'b00000
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`define load_mode_register 13'b0000001100001
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`define drive_strengh 1'b0
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`define dll_enable 1'b0
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`define ext_load_mode_register 13'b0000000000000
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`define chip_address 1
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`define reset_active_low 1'b1
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`define rcd_count_value 3'b001
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`define ras_count_value 4'b0101
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`define mrd_count_value 1'b0
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`define rp_count_value 3'b001
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`define rfc_count_value 6'b001001
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`define twr_count_value 3'b110
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`define twtr_count_value 3'b100
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`define max_ref_width 11
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`define max_ref_cnt 11'b10000000001
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`timescale 1ns/100ps
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