45 lines
1.8 KiB
Plaintext
45 lines
1.8 KiB
Plaintext
********************************************************************************************
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The sim folder has sample test_bench files to simulate the designs in Modelsim environment.
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This folder has the memory model, test bench, glbl file and required parameter files.
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Read the steps in this file before simulations are done.
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To run simulations for this sample configuration, user has to generate the RTL from the tool for the following GUI
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options.
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Data_width : 64
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HDL : Verilog or VHDL
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Memory configuration : x16
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DIMM/Component : Component
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Memory Part No : MT46V16M16XX-5
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Add test bench : Yes
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Use DCM : Yes
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Number of controllers : 1
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Number of Write pipelines : 4
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-----------------------------------------------For Verilog or VHDL----------------------------------------------------------
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1. After the rtl is generated, create the Model sim project file. Add all the rtl files from the rtl folder
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to the project Also add the memory model, test bench and glbl files from the sim folder.
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2. Compile the design.
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3. After successful compilation of design load the design using the following comamnd.
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vsim -t ps +notimingchecks -L ../Modeltech_6.1a/unisims_ver work.ddr1_test_tb glbl
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Note : User should set proper path for unisim verilog libraries
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4. After the design is successfully loaded, run the simulations and view the waveforms.
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Notes :
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1. To run simulations for different data widths and configurations, users should modify the test bench files
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with right memory models and design files.
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2. User must manually change the frequency of the test bench for proper simulations.
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3. Users should modify the test bench files for without test bench case.
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