53 lines
1.3 KiB
Verilog
53 lines
1.3 KiB
Verilog
//---------------------------------------------------------------------------
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// Behavioral model of a static ram chip
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//
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// Organization:
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//
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// 16 bit x 2**(adr_width-1)
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//---------------------------------------------------------------------------
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module sram16 #(
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parameter adr_width = 18
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) (
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input [adr_width-1:0] adr,
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inout [15:0] dat,
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input ub_n,
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input lb_n,
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input cs_n,
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input we_n,
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input oe_n
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);
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parameter dat_width = 16;
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//---------------------------------------------------------------------------
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// Actual RAM cells
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//---------------------------------------------------------------------------
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reg [7:0] mem_ub [0:1<<adr_width];
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reg [7:0] mem_lb [0:1<<adr_width];
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//---------------------------------------------------------------------------
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//
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//---------------------------------------------------------------------------
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wire [15:0] mem = { mem_ub[adr], mem_lb[adr] };
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wire [15:0] zzz = 16'bz;
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// Drive output
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assign dat = (!cs_n && !oe_n) ? mem : zzz;
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// Write to UB
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always @(*)
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if (!cs_n && !we_n && !ub_n)
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mem_ub[adr] = dat[15:8];
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// Write to LB
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always @(*)
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if (!cs_n && !we_n && !lb_n)
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mem_lb[adr] = dat[7:0];
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always @(*)
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if (!we_n && !oe_n)
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$display("Operational error in RamChip: OE and WE both active");
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endmodule
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