34 lines
875 B
Verilog
34 lines
875 B
Verilog
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.5.158.1 2007/03/09 18:13:02 patrickp Exp $
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///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995/2004 Xilinx, Inc.
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// All Right Reserved.
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 8.1i (I.13)
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// \ \ Description : Xilinx Functional Simulation Library Component
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// / / Global Clock Buffer
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// /___/ /\ Filename : BUFG.v
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// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004
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// \___\/\___\
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//
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// Revision:
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// 03/23/04 - Initial version.
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// End Revision
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`timescale 100 ps / 10 ps
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module BUFG (O, I);
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output O;
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input I;
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buf B1 (O, I);
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endmodule
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