103 lines
2.9 KiB
Verilog
103 lines
2.9 KiB
Verilog
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDDRRSE.v,v 1.15.48.1 2007/03/09 18:13:02 patrickp Exp $
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///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995/2004 Xilinx, Inc.
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// All Right Reserved.
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 8.1i (I.27)
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// \ \ Description : Xilinx Functional Simulation Library Component
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// / / Dual Data Rate D Flip-Flop with Synchronous Reset and Set and Clock Enable
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// /___/ /\ Filename : FDDRRSE.v
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// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004
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// \___\/\___\
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//
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// Revision:
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// 03/23/04 - Initial version.
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// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block.
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// 05/06/05 - Remove internal input data strobe and add to the output. (CR207678)
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// 10/20/05 - Add set & reset check to main block. (CR219794)
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// 10/28/05 - combine strobe block and data block. (CR220298).
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// 2/07/06 - Remove set & reset from main block and add specify block (CR225119)
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// 2/10/06 - Change Q from reg to wire (CR 225613)
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// End Revision
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`timescale 1 ps / 1 ps
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module FDDRRSE (Q, C0, C1, CE, D0, D1, R, S);
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parameter INIT = 1'h0;
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output Q;
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input C0, C1, CE, D0, D1, R, S;
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wire Q;
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reg q_out;
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reg q0_out, q1_out;
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reg C0_tmp, C1_tmp;
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initial begin
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q_out = INIT;
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q0_out = INIT;
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q1_out = INIT;
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C0_tmp = 0;
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C1_tmp = 0;
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end
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assign Q = q_out;
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always @(posedge C0)
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if (CE == 1 || R == 1 || S == 1) begin
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C0_tmp <= 1;
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C0_tmp <= #100 0;
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end
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always @(posedge C1)
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if (CE == 1 || R == 1 || S == 1) begin
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C1_tmp <= 1;
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C1_tmp <= #100 0;
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end
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always @(posedge C0)
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if (R)
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q0_out <= 0;
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else if (S)
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q0_out <= 1;
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else if (CE)
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q0_out <= D0;
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always @(posedge C1)
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if (R)
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q1_out <= 0;
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else if (S)
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q1_out <= 1;
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else if (CE)
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q1_out <= D1;
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always @(posedge C0_tmp or posedge C1_tmp )
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if (C1_tmp)
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q_out = q1_out;
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else
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q_out = q0_out;
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specify
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if (R)
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(posedge C0 => (Q +: 1'b0)) = (100, 100);
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if (!R && S)
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(posedge C0 => (Q +: 1'b1)) = (100, 100);
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if (!R && !S && CE)
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(posedge C0 => (Q +: D0)) = (100, 100);
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if (R)
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(posedge C1 => (Q +: 1'b0)) = (100, 100);
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if (!R && S)
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(posedge C1 => (Q +: 1'b1)) = (100, 100);
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if (!R && !S && CE)
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(posedge C1 => (Q +: D1)) = (100, 100);
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endspecify
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endmodule
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