114 lines
2.1 KiB
Verilog
114 lines
2.1 KiB
Verilog
`timescale 1ns / 1ps
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module sram_bus_TB;
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// inputs
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reg clk;
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reg [12:0] addr;
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reg nwe;
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reg ncs;
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reg noe;
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reg reset;
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// leds
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reg led;
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// Bidirs
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reg [7:0] sram_data$inout$reg ;
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// Instantiate the Unit Under Test (UUT)
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sram_bus uut ( .clk(clk), .reset(reset),
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.sram_data(sram_data), .addr(addr), .nwe(nwe),
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.ncs(ncs), .noe(noe)
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);
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parameter PERIOD = 20;
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parameter real DUTY_CYCLE = 0.5;
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parameter OFFSET = 0;
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parameter TSET = 3;
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parameter THLD = 3;
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parameter NWS = 3;
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parameter CAM_OFF = 4000;
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reg [15:0] i;
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reg [15:0] j;
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reg [15:0] k;
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reg [15:0] data_tx;
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event reset_trigger;
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event reset_done_trigger;
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initial begin // Reset the system, Start the image capture process
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forever begin
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@ (reset_trigger);
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@ (negedge clk);
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reset = 1;
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@ (negedge clk);
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reset = 0;
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-> reset_done_trigger;
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end
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end
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initial begin // Initialize Inputs
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clk = 0; addr = 0; nwe = 1; ncs = 1; noe = 1;
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end
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initial begin // Process for clk
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#OFFSET;
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forever
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begin
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clk = 1'b0;
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#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
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#(PERIOD*DUTY_CYCLE);
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end
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end
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initial begin: TEST_CASE
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#10 -> reset_trigger;
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@ (reset_done_trigger);
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// Write data to SRAM
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for(i=0; i<10; i=i+1) begin
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@ (posedge clk);
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ncs <= 0;
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addr <= i[9:0];
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repeat (TSET) begin
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@ (posedge clk);
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end
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nwe <= 0;
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sram_data$inout$reg <= i*2;
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repeat (NWS) begin
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@ (posedge clk);
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end
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nwe <= 1;
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repeat (THLD) begin
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@ (posedge clk);
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end
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ncs <= 1;
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sram_data$inout$reg = {16{1'bz}};
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end
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nwe = 1;
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//Read Data
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for(i=0; i<10; i=i+1) begin
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@ (posedge clk);
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ncs <= 0;
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addr <= i[9:0];
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repeat (TSET) begin
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@ (posedge clk);
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end
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noe <= 0;
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sram_data$inout$reg <= i;
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repeat (NWS) begin
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@ (posedge clk);
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end
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noe <= 1;
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repeat (THLD) begin
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@ (posedge clk);
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end
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ncs <= 1;
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sram_data$inout$reg = {16{1'bz}};
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end
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end
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endmodule
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