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243 lines
9.3 KiB
VHDL
243 lines
9.3 KiB
VHDL
-- TITLE: Plasma (CPU core with memory)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 6/4/02
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-- FILENAME: plasma.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- This entity combines the CPU core with memory and a UART.
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--
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-- Memory Map:
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-- 0x00000000 - 0x0000ffff Internal RAM (8KB)
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-- 0x10000000 - 0x100fffff External RAM (1MB)
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-- Access all Misc registers with 32-bit accesses
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-- 0x20000000 Uart Write (will pause CPU if busy)
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-- 0x20000000 Uart Read
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-- 0x20000010 IRQ Mask
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-- 0x20000020 IRQ Status
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-- 0x20000030 Peripheric 1
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-- 0x20000040 Peripheric 2
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-- 0x20000050 Peripheric 3
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-- 0x20000060 Peripheric 4
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-- IRQ bits:
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-- 1 ^UartWriteBusy
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-- 0 UartDataAvailable
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.mlite_pack.all;
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entity plasma is
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generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
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log_file : string := "UNUSED");
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port(clk_in : in std_logic;
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rst_in : in std_logic;
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uart_write : out std_logic;
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uart_read : in std_logic;
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addr : in std_logic_vector(12 downto 0);
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sram_data : in std_logic_vector(7 downto 0);
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nwe : in std_logic;
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noe : in std_logic;
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ncs : in std_logic;
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irq_pin : out std_logic;
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led : out std_logic
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);
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end; --entity plasma
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architecture logic of plasma is
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signal reset : std_logic;
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signal clk : std_logic;
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signal address_next : std_logic_vector(31 downto 2);
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signal byte_we_next : std_logic_vector(3 downto 0);
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signal cpu_address : std_logic_vector(31 downto 0);
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signal cpu_byte_we : std_logic_vector(3 downto 0);
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signal cpu_data_w : std_logic_vector(31 downto 0);
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signal cpu_data_r : std_logic_vector(31 downto 0);
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signal cpu_pause : std_logic;
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signal bus_dec : std_logic_vector(6 downto 0);
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signal data_read_uart : std_logic_vector(7 downto 0);
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signal data_read_pic : std_logic_vector(7 downto 0);
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signal write_enable : std_logic;
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signal mem_busy : std_logic;
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signal cs_pher : std_logic;
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signal cs_uart : std_logic;
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signal cs_pic : std_logic;
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signal cs_p1 : std_logic;
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signal cs_p2 : std_logic;
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signal cs_p3 : std_logic;
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signal cs_p4 : std_logic;
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signal uart_write_busy : std_logic;
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signal uart_data_avail : std_logic;
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signal irq_mask_reg : std_logic_vector(7 downto 0);
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signal irq_status : std_logic_vector(7 downto 0);
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signal irq : std_logic;
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signal cs_ram : std_logic;
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signal ram_byte_we : std_logic_vector(3 downto 0);
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signal ram_address : std_logic_vector(31 downto 2);
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signal ram_data_w : std_logic_vector(31 downto 0);
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signal ram_data_r : std_logic_vector(31 downto 0);
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begin
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--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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-- CLOCK DIVIDER
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--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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led <= not(rst_in);
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reset <= not(rst_in);
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irq_pin <= not(rst_in);
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clk_div: process(reset, clk, clk_in)
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begin
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if reset = '1' then
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clk <= '0';
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elsif rising_edge(clk_in) then
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clk <= not clk;
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end if;
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end process;
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write_enable <= '1' when cpu_byte_we /= "0000" else '0';
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cpu_pause <= (uart_write_busy and cs_uart and write_enable);
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--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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-- PROCESSOR
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--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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u1_cpu: mlite_cpu
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generic map (memory_type => memory_type)
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PORT MAP (
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clk => clk,
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reset_in => reset,
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intr_in => irq,
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address_next => address_next, --before rising_edge(clk)
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byte_we_next => byte_we_next,
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address => cpu_address(31 downto 2), --after rising_edge(clk)
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byte_we => cpu_byte_we,
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data_w => cpu_data_w,
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data_r => cpu_data_r,
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mem_pause => cpu_pause);
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--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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-- ADDRESS DECODER
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--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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cpu_address(1 downto 0) <= "00";
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addr_decoder: process (cpu_address)
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variable addr_dec : std_logic_vector(6 downto 0);
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begin
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addr_dec := cpu_address(30 downto 28) & cpu_address(7 downto 4);
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case addr_dec is
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when "0100000" => cs_uart <= '1'; cs_pic <= '0'; cs_p1 <= '0'; cs_p2 <= '0'; cs_p3 <= '0'; cs_p4 <= '0';
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when "0100001" => cs_uart <= '0'; cs_pic <= '1'; cs_p1 <= '0'; cs_p2 <= '0'; cs_p3 <= '0'; cs_p4 <= '0';
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when "0100010" => cs_uart <= '0'; cs_pic <= '1'; cs_p1 <= '0'; cs_p2 <= '0'; cs_p3 <= '0'; cs_p4 <= '0';
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when "0100011" => cs_uart <= '0'; cs_pic <= '0'; cs_p1 <= '1'; cs_p2 <= '0'; cs_p3 <= '0'; cs_p4 <= '0';
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when "0100100" => cs_uart <= '0'; cs_pic <= '0'; cs_p1 <= '0'; cs_p2 <= '1'; cs_p3 <= '0'; cs_p4 <= '0';
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when "0100101" => cs_uart <= '0'; cs_pic <= '0'; cs_p1 <= '0'; cs_p2 <= '0'; cs_p3 <= '1'; cs_p4 <= '0';
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when "0100110" => cs_uart <= '0'; cs_pic <= '0'; cs_p1 <= '0'; cs_p2 <= '0'; cs_p3 <= '0'; cs_p4 <= '1';
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when others => cs_uart <= '0'; cs_pic <= '0'; cs_p1 <= '0'; cs_p2 <= '0'; cs_p3 <= '0'; cs_p4 <= '0';
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end case;
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end process;
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--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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-- BUS MULTIPLEXOR
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--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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bus_mux: process (cpu_address, ram_data_r, data_read_uart, data_read_pic)
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variable bus_dec : std_logic_vector(4 downto 0);
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begin
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bus_dec := cpu_address(29) & cpu_address(7 downto 4);
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case bus_dec is
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when "00000" | "00001" | "00010" | "00011" | "00100" | "00101" | "00110" | "00111" |
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"01000" | "01001" | "01010" | "01011" | "01100" | "01101" | "01110" | "01111"
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=> cpu_data_r <= ram_data_r;
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when "10000" => cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
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when "10001" => cpu_data_r <= ZERO(31 downto 8) & data_read_pic;
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when "10010" => cpu_data_r <= ZERO(31 downto 8) & data_read_pic;
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when "10011" => cpu_data_r <= ZERO;
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when "10100" => cpu_data_r <= ZERO;
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when "10101" => cpu_data_r <= ZERO;
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when "10110" => cpu_data_r <= ZERO;
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when others => cpu_data_r <= ZERO;
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end case;
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-- end if;
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end process;
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--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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-- PIC
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--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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pic_proc: process(clk, reset, cpu_address, cs_pic, cpu_pause, cpu_byte_we, irq_mask_reg, irq_status, cpu_data_w,
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uart_write_busy, uart_data_avail)
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begin
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irq_status <= ZERO(5 downto 0) & not uart_write_busy & uart_data_avail;
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if cs_pic = '1' and cpu_byte_we = "0000" then
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case cpu_address(5 downto 4) is
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when "01" => data_read_pic <= irq_mask_reg;
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when "10" => data_read_pic <= irq_status;
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when others => data_read_pic <= ZERO(7 downto 0);
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end case;
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end if;
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if reset = '1' then
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irq_mask_reg <= ZERO(7 downto 0);
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elsif rising_edge(clk) then
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if cpu_pause = '0' then
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if cs_pic = '1' and cpu_byte_we = "1111" then
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if cpu_address(6 downto 4) = "001" then
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irq_mask_reg <= cpu_data_w(7 downto 0);
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end if;
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end if;
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end if;
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end if;
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if (irq_status and irq_mask_reg) /= ZERO(7 downto 0) then
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irq <= '1';
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else
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irq <= '0';
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end if;
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end process;
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--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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-- RAM
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--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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cs_ram <= '1' when address_next(30 downto 28) = "000" else '0';
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ram_address(31 downto 2) <= ZERO(31 downto 13) & address_next(12 downto 2);
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u2_ram: ram
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generic map (memory_type => memory_type)
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port map (
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clk => clk,
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enable => cs_ram,
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write_byte_enable => byte_we_next,
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address => ram_address,
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data_write => cpu_data_w,
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data_read => ram_data_r);
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--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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-- UART
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--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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u3_uart: uart
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generic map (log_file => log_file)
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port map(
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clk => clk,
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reset => reset,
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cs => cs_uart,
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nRdWr => cpu_byte_we(0),
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data_in => cpu_data_w(7 downto 0),
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data_out => data_read_uart,
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uart_read => uart_read,
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uart_write => uart_write,
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busy_write => uart_write_busy,
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data_avail => uart_data_avail);
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end; --architecture logic
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