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71 lines
2.2 KiB
VHDL
71 lines
2.2 KiB
VHDL
---------------------------------------------------------------------
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-- TITLE: Test Bench
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 4/21/01
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-- FILENAME: tbench.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- This entity provides a test bench for testing the Plasma CPU core.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity plasma_tb is
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end; --entity tbench
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architecture logic of plasma_tb is
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constant memory_type : string := "TRI_PORT_X";
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signal clk_in : std_logic := '1';
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signal rst_in : std_logic := '0';
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signal addr : std_logic_vector(12 downto 0);
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signal sram_data : std_logic_vector(7 downto 0);
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signal nwe : std_logic;
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signal noe : std_logic;
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signal ncs : std_logic;
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signal irq_pin : std_logic;
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signal led : std_logic;
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signal TxD : std_logic;
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signal RxD : std_logic;
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component plasma
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port(clk_in : in std_logic;
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rst_in : in std_logic;
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uart_write : out std_logic;
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uart_read : in std_logic;
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addr : in std_logic_vector(12 downto 0);
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sram_data : in std_logic_vector(7 downto 0);
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nwe : in std_logic;
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noe : in std_logic;
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ncs : in std_logic;
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irq_pin : out std_logic;
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led : out std_logic);
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end component; --plasma
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begin --architecture
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clk_in <= not clk_in after 50 ns;
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rst_in <= '1' after 500 ns;
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RxD <= '1';
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u1_plasma: plasma
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PORT MAP (
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clk_in => clk_in,
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rst_in => rst_in,
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uart_read => RxD,
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uart_write => TxD,
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addr => addr,
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sram_data => sram_data,
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nwe => nwe,
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noe => noe,
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ncs => ncs,
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irq_pin => irq_pin,
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led => led
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);
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end; --architecture logic
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