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171 lines
6.2 KiB
VHDL
171 lines
6.2 KiB
VHDL
---------------------------------------------------------------------
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-- TITLE: UART
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 5/29/02
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-- FILENAME: uart.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- Implements the UART.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_unsigned.all;
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use std.textio.all;
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use work.mlite_pack.all;
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entity uart is
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generic(log_file : string := "UNUSED");
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port(clk : in std_logic;
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reset : in std_logic;
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cs : in std_logic;
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nRdWr : in std_logic;
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data_in : in std_logic_vector(7 downto 0);
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data_out : out std_logic_vector(7 downto 0);
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uart_read : in std_logic;
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uart_write : out std_logic;
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busy_write : out std_logic;
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data_avail : out std_logic);
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end; --entity uart
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architecture logic of uart is
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signal delay_write_reg : std_logic_vector(9 downto 0);
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signal bits_write_reg : std_logic_vector(3 downto 0);
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signal data_write_reg : std_logic_vector(8 downto 0);
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signal delay_read_reg : std_logic_vector(9 downto 0);
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signal bits_read_reg : std_logic_vector(3 downto 0);
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signal data_read_reg : std_logic_vector(7 downto 0);
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signal data_save_reg : std_logic_vector(17 downto 0);
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signal busy_write_sig : std_logic;
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signal read_value_reg : std_logic_vector(6 downto 0);
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signal uart_read2 : std_logic;
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signal enable_read : std_logic;
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signal enable_write : std_logic;
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begin
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interface_proc: process(cs, nRdWr)
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begin
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if cs = '1' then
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if nRdWr = '1' then
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enable_read <= '0';
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enable_write <= '1';
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else
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enable_read <= '1';
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enable_write <= '0';
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end if;
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else
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enable_read <= '0';
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enable_write <= '0';
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end if;
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end process;
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uart_proc: process(clk, reset, enable_read, enable_write, data_in,
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data_write_reg, bits_write_reg, delay_write_reg,
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data_read_reg, bits_read_reg, delay_read_reg,
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data_save_reg, read_value_reg, uart_read2,
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busy_write_sig, uart_read)
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constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
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-- "0100011110"; --33MHz/2/57600Hz = 0x11e
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-- "1101100100"; --50MHz/57600Hz = 0x364
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"0110110010"; --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2
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-- "0011011001"; --12.5MHz/57600Hz = 0xd9
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-- "0000000100"; --for debug (shorten read_value_reg)
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begin
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uart_read2 <= read_value_reg(read_value_reg'length - 1);
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if reset = '1' then
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data_write_reg <= ZERO(8 downto 1) & '1';
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bits_write_reg <= "0000";
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delay_write_reg <= ZERO(9 downto 0);
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read_value_reg <= ONES(read_value_reg'length-1 downto 0);
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data_read_reg <= ZERO(7 downto 0);
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bits_read_reg <= "0000";
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delay_read_reg <= ZERO(9 downto 0);
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data_save_reg <= ZERO(17 downto 0);
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elsif rising_edge(clk) then
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--Write UART
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if bits_write_reg = "0000" then --nothing left to write?
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if enable_write = '1' then
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delay_write_reg <= ZERO(9 downto 0); --delay before next bit
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bits_write_reg <= "1010"; --number of bits to write
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data_write_reg <= data_in & '0'; --remember data & start bit
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end if;
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else
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if delay_write_reg /= COUNT_VALUE then
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delay_write_reg <= delay_write_reg + 1; --delay before next bit
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else
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delay_write_reg <= ZERO(9 downto 0); --reset delay
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bits_write_reg <= bits_write_reg - 1; --bits left to write
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data_write_reg <= '1' & data_write_reg(8 downto 1);
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end if;
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end if;
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--Average uart_read signal
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if uart_read = '1' then
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if read_value_reg /= ONES(read_value_reg'length - 1 downto 0) then
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read_value_reg <= read_value_reg + 1;
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end if;
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else
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if read_value_reg /= ZERO(read_value_reg'length - 1 downto 0) then
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read_value_reg <= read_value_reg - 1;
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end if;
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end if;
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--Read UART
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if delay_read_reg = ZERO(9 downto 0) then --done delay for read?
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if bits_read_reg = "0000" then --nothing left to read?
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if uart_read2 = '0' then --wait for start bit
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delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period
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bits_read_reg <= "1001"; --bits left to read
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end if;
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else
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delay_read_reg <= COUNT_VALUE; --initialize delay
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bits_read_reg <= bits_read_reg - 1; --bits left to read
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data_read_reg <= uart_read2 & data_read_reg(7 downto 1);
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end if;
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else
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delay_read_reg <= delay_read_reg - 1; --delay
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end if;
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--Control character buffer
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if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then
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if data_save_reg(8) = '0' or
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(enable_read = '1' and data_save_reg(17) = '0') then
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--Empty buffer
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data_save_reg(8 downto 0) <= '1' & data_read_reg;
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else
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--Second character in buffer
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data_save_reg(17 downto 9) <= '1' & data_read_reg;
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if enable_read = '1' then
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data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
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end if;
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end if;
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elsif enable_read = '1' then
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data_save_reg(17) <= '0'; --data_available
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data_save_reg(8 downto 0) <= data_save_reg(17 downto 9);
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end if;
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end if; --rising_edge(clk)
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uart_write <= data_write_reg(0);
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if bits_write_reg /= "0000"
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-- Comment out the following line for full UART simulation (much slower)
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and log_file = "UNUSED"
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then
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busy_write_sig <= '1';
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else
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busy_write_sig <= '0';
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end if;
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busy_write <= busy_write_sig;
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data_avail <= data_save_reg(8);
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data_out <= data_save_reg(7 downto 0);
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end process; --uart_proc
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end; --architecture logic
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