18 lines
522 B
VHDL
18 lines
522 B
VHDL
library verilog;
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use verilog.vl_types.all;
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entity sram_bus is
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generic(
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B : integer := 7
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);
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port(
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clk : in vl_logic;
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sram_data : inout vl_logic_vector;
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addr : in vl_logic_vector(12 downto 0);
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nwe : in vl_logic;
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ncs : in vl_logic;
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noe : in vl_logic;
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reset : in vl_logic;
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led : out vl_logic
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);
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end sram_bus;
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