nn-usb-fpga/Examples/sram/logic/simulation/work/sram_bus_@t@b_v/_primary.vhd

library verilog;
use verilog.vl_types.all;
entity sram_bus_TB_v is
    generic(
        PERIOD          : integer := 20;
        DUTY_CYCLE      : real    := 0.500000;
        OFFSET          : integer := 0;
        TSET            : integer := 3;
        THLD            : integer := 3;
        NWS             : integer := 3;
        CAM_OFF         : integer := 4000
    );
end sram_bus_TB_v;