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72 lines
2.5 KiB
Verilog
72 lines
2.5 KiB
Verilog
// =============================================================================
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// COPYRIGHT NOTICE
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// Copyright 2006 (c) Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// This confidential and proprietary software may be used only as authorised by
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// a licensing agreement from Lattice Semiconductor Corporation.
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// The entire notice above must be reproduced on all authorized copies and
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// copies may only be made to the extent permitted by a licensing agreement from
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// Lattice Semiconductor Corporation.
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//
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// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
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// 5555 NE Moore Court 408-826-6000 (other locations)
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// Hillsboro, OR 97124 web : http://www.latticesemi.com/
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// U.S.A email: techsupport@latticesemi.com
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// =============================================================================/
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// FILE DETAILS
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// Project : LatticeMico32
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// File : lm32_logic_op.v
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// Title : Logic operations (and / or / not etc)
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// Dependencies : lm32_include.v
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// Version : 6.1.17
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// =============================================================================
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`include "lm32_include.v"
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/////////////////////////////////////////////////////
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// Module interface
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/////////////////////////////////////////////////////
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module lm32_logic_op (
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// ----- Inputs -------
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logic_op_x,
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operand_0_x,
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operand_1_x,
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// ----- Outputs -------
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logic_result_x
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);
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/////////////////////////////////////////////////////
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// Inputs
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/////////////////////////////////////////////////////
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input [`LM32_LOGIC_OP_RNG] logic_op_x;
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input [`LM32_WORD_RNG] operand_0_x;
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input [`LM32_WORD_RNG] operand_1_x;
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/////////////////////////////////////////////////////
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// Outputs
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/////////////////////////////////////////////////////
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output [`LM32_WORD_RNG] logic_result_x;
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reg [`LM32_WORD_RNG] logic_result_x;
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/////////////////////////////////////////////////////
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// Internal nets and registers
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/////////////////////////////////////////////////////
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integer logic_idx;
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/////////////////////////////////////////////////////
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// Combinational Logic
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/////////////////////////////////////////////////////
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always @*
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begin
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for(logic_idx = 0; logic_idx < `LM32_WORD_WIDTH; logic_idx = logic_idx + 1)
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logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}];
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end
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endmodule
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