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106 lines
3.6 KiB
Verilog
106 lines
3.6 KiB
Verilog
// =============================================================================
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// COPYRIGHT NOTICE
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// Copyright 2006 (c) Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// This confidential and proprietary software may be used only as authorised by
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// a licensing agreement from Lattice Semiconductor Corporation.
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// The entire notice above must be reproduced on all authorized copies and
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// copies may only be made to the extent permitted by a licensing agreement from
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// Lattice Semiconductor Corporation.
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//
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// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
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// 5555 NE Moore Court 408-826-6000 (other locations)
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// Hillsboro, OR 97124 web : http://www.latticesemi.com/
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// U.S.A email: techsupport@latticesemi.com
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// =============================================================================/
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// FILE DETAILS
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// Project : LatticeMico32
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// File : lm32_ram.v
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// Title : Pseudo dual-port RAM.
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// Version : 6.1.17
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// =============================================================================
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`include "lm32_include.v"
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/////////////////////////////////////////////////////
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// Module interface
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/////////////////////////////////////////////////////
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module lm32_ram (
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// ----- Inputs -------
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read_clk,
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write_clk,
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reset,
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enable_read,
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read_address,
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enable_write,
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write_address,
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write_data,
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write_enable,
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// ----- Outputs -------
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read_data
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);
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/////////////////////////////////////////////////////
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// Parameters
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/////////////////////////////////////////////////////
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parameter data_width = 1; // Width of the data ports
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parameter address_width = 1; // Width of the address ports
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/////////////////////////////////////////////////////
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// Inputs
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/////////////////////////////////////////////////////
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input read_clk; // Read clock
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input write_clk; // Write clock
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input reset; // Reset
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input enable_read; // Access enable
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input [address_width-1:0] read_address; // Read/write address
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input enable_write; // Access enable
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input [address_width-1:0] write_address;// Read/write address
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input [data_width-1:0] write_data; // Data to write to specified address
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input write_enable; // Write enable
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/////////////////////////////////////////////////////
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// Outputs
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/////////////////////////////////////////////////////
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output [data_width-1:0] read_data; // Data read from specified addess
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wire [data_width-1:0] read_data;
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/////////////////////////////////////////////////////
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// Internal nets and registers
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/////////////////////////////////////////////////////
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reg [data_width-1:0] mem[0:(1<<address_width)-1]; // The RAM
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reg [address_width-1:0] ra; // Registered read address
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/////////////////////////////////////////////////////
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// Combinational Logic
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/////////////////////////////////////////////////////
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// Read port
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assign read_data = mem[ra];
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/////////////////////////////////////////////////////
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// Sequential Logic
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/////////////////////////////////////////////////////
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// Write port
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always @(posedge write_clk)
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begin
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if ((write_enable == `TRUE) && (enable_write == `TRUE))
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mem[write_address] <= write_data;
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end
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// Register read address for use on next cycle
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always @(posedge read_clk)
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begin
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if (enable_read)
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ra <= read_address;
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end
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endmodule
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