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add jtag-serial cable, xc3slx16 ucf patches

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This commit is contained in:
Xiangfu 2013-07-02 02:03:39 +08:00
parent 463b8536a8
commit 8dc9141cd3
2 changed files with 112 additions and 0 deletions
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25
xc3sprog/patches/0001-add-qi-jtag-serial-cable.patch Normal file
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@ -0,0 +1,25 @@
From bbd42d8369343a782317c25c2be933e77956fc26 Mon Sep 17 00:00:00 2001
From: Xiangfu <xiangfu@openmobilefree.net>
Date: Mon, 1 Jul 2013 20:19:01 +0800
Subject: [PATCH 1/2] add qi-jtag-serial cable
---
cablelist.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/cablelist.txt b/cablelist.txt
index 2d59dda..db37967 100644
--- a/cablelist.txt
+++ b/cablelist.txt
@@ -6,6 +6,8 @@
# Max_Freq == 0 mean use maximum speed of device
# Use 1500000 for all cable connected cables and max for all on board cables
+qi ftdi 1500000 0x20b7:0x0713:
+qijtag ftdi 1500000 0x20b7:0x0713:FTDIJTAG:1:0x00:0x10:0x00:0x00
ftdi ftdi 1500000 0x0403:0x6010:
minila ftdi 800000 0x0403:0x6010:
ft232h ftdi 1500000 0x0403:0x6014:
--
1.8.1.2

87
xc3sprog/patches/0002-add-xc6slx16-ucf-and-a-Makefile-for-xilinx-tools.patch Normal file
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@ -0,0 +1,87 @@
From 1bdad90649f380ba652b6ff522646345c0b575c6 Mon Sep 17 00:00:00 2001
From: Xiangfu <xiangfu@openmobilefree.net>
Date: Mon, 1 Jul 2013 20:19:29 +0800
Subject: [PATCH 2/2] add xc6slx16 ucf and a Makefile for xilinx tools
---
bscan_spi/Makefile | 56 ++++++++++++++++++++++++++++++++++++++
bscan_spi/bscan_s6_spi_isf_ext.ucf | 4 +++
2 files changed, 60 insertions(+)
create mode 100644 bscan_spi/Makefile
create mode 100644 bscan_spi/bscan_s6_spi_isf_ext.ucf
diff --git a/bscan_spi/Makefile b/bscan_spi/Makefile
new file mode 100644
index 0000000..59dad6b
--- /dev/null
+++ b/bscan_spi/Makefile
@@ -0,0 +1,56 @@
+#
+# Author: Xiangfu Liu
+#
+# This is free and unencumbered software released into the public domain.
+# For details see the UNLICENSE file at the root of the source tree.
+#
+
+all: bscan_s6_spi_isf_ext.bit
+
+# Build for m1
+#FPGA_TARGET ?= xc6slx45-fgg484-2
+
+# Build for mini-slx9 board tqg144/ftg256/csg324
+#FPGA_TARGET ?= xc6slx9-2-csg324
+#FPGA_TARGET ?= xc6slx9-2-ftg256
+FPGA_TARGET ?= xc6slx16-2-ftg256
+
+%.bit: %-routed.ncd
+# -d disables DRC
+# -b creates rawbits file .rbt
+# -l creates logic allocation file .ll
+# -w overwrite existing output file
+# "-g compress" enables compression
+ if test -f $<; then bitgen -b -l -w $< $@; fi
+ mkdir -p bits
+ cp $@ bits/$(FPGA_TARGET).$@
+
+%.ncd: %.xdl
+ -xdl -xdl2ncd $<
+
+%-routed.ncd: %.ncd
+ par -w $< $@
+
+%.ncd: %.ngd
+ map -w $<
+
+%.ngd: %.ucf %.ngc
+ ngdbuild -uc $< $(@:.ngd=.ngc)
+
+%.ngc: %.xst
+ xst -ifn $<
+
+%.xst: %.prj
+ echo run > $@
+ echo -ifn $< >> $@
+ echo -top top >> $@
+ echo -ifmt MIXED >> $@
+ echo -opt_mode SPEED >> $@
+ echo -opt_level 1 >> $@
+ echo -ofn $(<:.prj=.ngc) >> $@
+ echo -p $(FPGA_TARGET) >> $@
+
+%.prj: %.v
+ for i in `echo $^`; do \
+ echo "verilog $(basename $<) $$i" >> $@; \
+ done
diff --git a/bscan_spi/bscan_s6_spi_isf_ext.ucf b/bscan_spi/bscan_s6_spi_isf_ext.ucf
new file mode 100644
index 0000000..48098cd
--- /dev/null
+++ b/bscan_spi/bscan_s6_spi_isf_ext.ucf
@@ -0,0 +1,4 @@
+net "MISO" LOC = "P10";
+net "MOSI" LOC = "T10";
+net "DRCK1" LOC= "R11";
+net "CSB" LOC = "T3";
--
1.8.1.2