--- linux-mips-cvs/arch/mips/mm/c-r4k.c	2004-11-03 17:43:07.000000000 +0100
+++ linux-cache/arch/mips/mm/c-r4k.c	2005-03-06 23:39:53.000000000 +0100
@@ -1031,9 +1031,34 @@
 	c->options |= MIPS_CPU_SUBSET_CACHES;
 }
 
+#if defined(CONFIG_BCM4310)
+static void __init _change_cachability(u32 cm)
+{
+	struct cpuinfo_mips *c = &current_cpu_data;
+
+	change_c0_config(CONF_CM_CMASK, cm);
+	if ((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) ==
+			(PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) {
+				cm = read_c0_diag();
+				/* Enable icache */
+                cm |= (1 << 31);
+                /* Enable dcache */
+                cm |= (1 << 30);
+                write_c0_diag(cm);
+	}
+}
+
+static void (*change_cachability)(u32);
+#endif
+
 static inline void coherency_setup(void)
 {
+#if defined(CONFIG_BCM4310)
+	change_cachability = (void (*)(u32)) KSEG1ADDR((unsigned long)(_change_cachability));
+	change_cachability(CONF_CM_DEFAULT);
+#else
 	change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
+#endif
 
 	/*
 	 * c0_status.cu=0 specifies that updates by the sc instruction use
