mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-16 08:56:15 +02:00
90 lines
2.4 KiB
Diff
90 lines
2.4 KiB
Diff
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -195,7 +195,6 @@ config MIPS_MALTA
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select I8259
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select MIPS_BOARDS_GEN
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select MIPS_BONITO64
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- select MIPS_CPU_SCACHE
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select PCI_GT64XXX_PCI0
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select MIPS_MSC
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select SWAP_IO_SPACE
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@@ -1461,13 +1460,6 @@ config IP22_CPU_SCACHE
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bool
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select BOARD_SCACHE
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-#
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-# Support for a MIPS32 / MIPS64 style S-caches
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-#
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-config MIPS_CPU_SCACHE
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- bool
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- select BOARD_SCACHE
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-
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config R5000_CPU_SCACHE
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bool
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select BOARD_SCACHE
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--- a/arch/mips/kernel/cpu-probe.c
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+++ b/arch/mips/kernel/cpu-probe.c
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@@ -753,6 +753,8 @@ static inline void cpu_probe_mips(struct
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case PRID_IMP_25KF:
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c->cputype = CPU_25KF;
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__cpu_name[cpu] = "MIPS 25Kc";
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+ /* Probe for L2 cache */
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+ c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
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break;
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case PRID_IMP_34K:
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c->cputype = CPU_34K;
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--- a/arch/mips/mm/Makefile
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+++ b/arch/mips/mm/Makefile
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@@ -32,6 +32,5 @@ obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-oct
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obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
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obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
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obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
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-obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
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EXTRA_CFLAGS += -Werror
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--- a/arch/mips/mm/c-r4k.c
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+++ b/arch/mips/mm/c-r4k.c
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@@ -1135,7 +1135,6 @@ static void __init loongson2_sc_init(voi
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extern int r5k_sc_init(void);
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extern int rm7k_sc_init(void);
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-extern int mips_sc_init(void);
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static void __cpuinit setup_scache(void)
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{
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@@ -1189,29 +1188,17 @@ static void __cpuinit setup_scache(void)
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#endif
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default:
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- if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
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- c->isa_level == MIPS_CPU_ISA_M32R2 ||
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- c->isa_level == MIPS_CPU_ISA_M64R1 ||
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- c->isa_level == MIPS_CPU_ISA_M64R2) {
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-#ifdef CONFIG_MIPS_CPU_SCACHE
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- if (mips_sc_init ()) {
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- scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
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- printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
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- scache_size >> 10,
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- way_string[c->scache.ways], c->scache.linesz);
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- }
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-#else
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- if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
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- panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
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-#endif
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- return;
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- }
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sc_present = 0;
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}
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if (!sc_present)
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return;
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+ if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
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+ c->isa_level == MIPS_CPU_ISA_M64R1) &&
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+ !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
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+ panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
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+
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/* compute a couple of other cache variables */
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c->scache.waysize = scache_size / c->scache.ways;
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