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109 lines
2.7 KiB
C
109 lines
2.7 KiB
C
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/*
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* Misc useful routines to access NIC local SROM/OTP .
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*
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* Copyright 2006, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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* $Id: bcmsrom.h,v 1.1.1.13 2006/04/15 01:29:08 michael Exp $
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*/
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#ifndef _bcmsrom_h_
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#define _bcmsrom_h_
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/* Maximum srom: 4 Kilobits == 512 bytes */
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#define SROM_MAX 512
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/* SROM Rev 4: Reallocate the software part of the srom to accomodate
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* MIMO features. It assumes up to two PCIE functions and 440 bytes
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* of useable srom i.e. the useable storage in chips with OTP that
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* implements hardware redundancy.
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*/
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#define SROM4_WORDS 220
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#define SROM4_SIGN 32
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#define SROM4_SIGNATURE 0x5372
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#define SROM4_BREV 33
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#define SROM4_BFL0 34
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#define SROM4_BFL1 35
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#define SROM4_BFL2 36
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#define SROM4_BFL3 37
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#define SROM4_MACHI 38
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#define SROM4_MACMID 39
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#define SROM4_MACLO 40
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#define SROM4_CCODE 41
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#define SROM4_REGREV 42
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#define SROM4_LEDBH10 43
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#define SROM4_LEDBH32 44
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#define SROM4_LEDDC 45
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#define SROM4_AA 46
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#define SROM4_AA2G_MASK 0x00ff
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#define SROM4_AA2G_SHIFT 0
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#define SROM4_AA5G_MASK 0xff00
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#define SROM4_AA5G_SHIFT 8
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#define SROM4_AG10 47
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#define SROM4_AG32 48
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#define SROM4_TXPID2G 49
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#define SROM4_TXPID5G 51
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#define SROM4_TXPID5GL 53
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#define SROM4_TXPID5GH 55
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/* Per-path fields */
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#define MAX_PATH 4
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#define SROM4_PATH0 64
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#define SROM4_PATH1 87
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#define SROM4_PATH2 110
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#define SROM4_PATH3 133
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#define SROM4_2G_ITT_MAXP 0
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#define SROM4_2G_PA 1
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#define SROM4_5G_ITT_MAXP 5
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#define SROM4_5GLH_MAXP 6
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#define SROM4_5G_PA 7
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#define SROM4_5GL_PA 11
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#define SROM4_5GH_PA 15
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/* Fields in the ITT_MAXP and 5GLH_MAXP words */
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#define B2G_MAXP_MASK 0xff
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#define B2G_ITT_SHIFT 8
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#define B5G_MAXP_MASK 0xff
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#define B5G_ITT_SHIFT 8
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#define B5GH_MAXP_MASK 0xff
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#define B5GL_MAXP_SHIFT 8
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/* All the miriad power offsets */
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#define SROM4_2G_CCKPO 156
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#define SROM4_2G_OFDMPO 157
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#define SROM4_5G_OFDMPO 159
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#define SROM4_5GL_OFDMPO 161
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#define SROM4_5GH_OFDMPO 163
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#define SROM4_2G_MCSPO 165
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#define SROM4_5G_MCSPO 173
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#define SROM4_5GL_MCSPO 181
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#define SROM4_5GH_MCSPO 189
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#define SROM4_CCDPO 197
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#define SROM4_STBCPO 198
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#define SROM4_BW40PO 199
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#define SROM4_BWDUPPO 200
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extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, uint *count);
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extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
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extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
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#endif /* _bcmsrom_h_ */
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