2007-05-05 01:13:42 +03:00
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/*
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* Broadcom SiliconBackplane MIPS definitions
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*
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* SB MIPS cores are custom MIPS32 processors with SiliconBackplane
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* OCP interfaces. The CP0 processor ID is 0x00024000, where bits
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* 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
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* interface. The core revision is stored in the SB ID register in SB
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* configuration space.
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*
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2008-01-06 21:28:07 +02:00
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* Copyright 2007, Broadcom Corporation
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2007-05-05 01:13:42 +03:00
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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2008-01-06 21:28:07 +02:00
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* $Id$
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2007-05-05 01:13:42 +03:00
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*/
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#ifndef _sbhndmips_h_
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#define _sbhndmips_h_
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#include <mipsinc.h>
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#ifndef _LANGUAGE_ASSEMBLY
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/* cpp contortions to concatenate w/arg prescan */
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#ifndef PAD
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#define _PADLINE(line) pad ## line
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#define _XSTR(line) _PADLINE(line)
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#define PAD _XSTR(__LINE__)
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#endif /* PAD */
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typedef volatile struct {
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uint32 corecontrol;
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uint32 PAD[2];
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uint32 biststatus;
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uint32 PAD[4];
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uint32 intstatus;
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uint32 intmask;
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uint32 timer;
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} mipsregs_t;
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#endif /* _LANGUAGE_ASSEMBLY */
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#endif /* _sbhndmips_h_ */
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