qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2024-12-27 21:23:19 +02:00
Code
320dc1ed40
openwrt-xburst/target/linux/etrax/patches/cris/010-multi-target-build.patch

1974 lines
57 KiB
Diff
Raw Normal View History

add initial support for the crisarchitecture used on foxboards to openwrt git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7439 3c298f89-4303-0410-b956-a3cf2f4a3e73
2007-06-02 03:46:02 +03:00
diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/Makefile linux-2.6.19.2/arch/cris/arch-v10/boot/Makefile
--- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/Makefile 2007-05-28 16:28:34.000000000 +0200
+++ linux-2.6.19.2/arch/cris/arch-v10/boot/Makefile 2007-05-28 17:24:26.000000000 +0200
@@ -5,7 +5,7 @@
OBJCOPY = /usr/local/cris/objcopy-cris
OBJCOPYFLAGS = -O binary --remove-section=.bss
-subdir- := compressed rescue
+subdir- := compressed
targets := Image
$(obj)/Image: vmlinux FORCE
@@ -14,8 +14,12 @@
$(obj)/compressed/vmlinux: $(obj)/Image FORCE
$(Q)$(MAKE) $(build)=$(obj)/compressed $@
- $(Q)$(MAKE) $(build)=$(obj)/rescue $(obj)/rescue/rescue.bin
$(obj)/zImage: $(obj)/compressed/vmlinux
@cp $< $@
+ @cp $(obj)/compressed/vmlinux $(obj)/zImage_custom
+ @cp $(obj)/compressed/vmlinux_MCM $(obj)/zImage_MCM
+ @cp $(obj)/compressed/vmlinux_416 $(obj)/zImage_416
+ @cp $(obj)/compressed/vmlinux_816 $(obj)/zImage_816
+ @cp $(obj)/compressed/vmlinux_832 $(obj)/zImage_832
@echo ' Kernel: $@ is ready'
diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/Makefile linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/Makefile
--- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/Makefile 2007-05-28 16:28:34.000000000 +0200
+++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/Makefile 2007-05-28 17:03:02.000000000 +0200
@@ -17,18 +17,34 @@
$(obj)/decompress.o: $(OBJECTS) FORCE
$(call if_changed,ld)
+ $(LD) $(LDFLAGS) arch/cris/boot/compressed/head_MCM.o arch/cris/boot/compressed/misc.o -o arch/cris/boot/compressed/decompress_MCM.o
+ $(LD) $(LDFLAGS) arch/cris/boot/compressed/head_416.o arch/cris/boot/compressed/misc.o -o arch/cris/boot/compressed/decompress_416.o
+ $(LD) $(LDFLAGS) arch/cris/boot/compressed/head_816.o arch/cris/boot/compressed/misc.o -o arch/cris/boot/compressed/decompress_816.o
+ $(LD) $(LDFLAGS) arch/cris/boot/compressed/head_832.o arch/cris/boot/compressed/misc.o -o arch/cris/boot/compressed/decompress_832.o
$(obj)/decompress.bin: $(obj)/decompress.o FORCE
$(call if_changed,objcopy)
+ $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/decompress_MCM.o $(obj)/decompress_MCM.bin
+ $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/decompress_416.o $(obj)/decompress_416.bin
+ $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/decompress_816.o $(obj)/decompress_816.bin
+ $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/decompress_832.o $(obj)/decompress_832.bin
+
+$(obj)/head.o: $(obj)/head.S .config FORCE
+ /usr/local/cris/gcc-cris -melf -Iinclude -include include/linux/autoconf.h -D__ASSEMBLY__ -traditional -c $< -o $@
+ /usr/local/cris/gcc-cris -melf -Iinclude -include include/linux/autoconf.h -D__ASSEMBLY__ -traditional -c arch/cris/boot/compressed/head_MCM.S -o arch/cris/boot/compressed/head_MCM.o
+ /usr/local/cris/gcc-cris -melf -Iinclude -include include/linux/autoconf.h -D__ASSEMBLY__ -traditional -c arch/cris/boot/compressed/head_416.S -o arch/cris/boot/compressed/head_416.o
+ /usr/local/cris/gcc-cris -melf -Iinclude -include include/linux/autoconf.h -D__ASSEMBLY__ -traditional -c arch/cris/boot/compressed/head_816.S -o arch/cris/boot/compressed/head_816.o
+ /usr/local/cris/gcc-cris -melf -Iinclude -include include/linux/autoconf.h -D__ASSEMBLY__ -traditional -c arch/cris/boot/compressed/head_832.S -o arch/cris/boot/compressed/head_832.o
-$(obj)/head.o: $(obj)/head.S .config
- /usr/local/cris/gcc-cris -melf $(LINUXINCLUDE) -D__ASSEMBLY__ -traditional -c $< -o $@
-
-$(obj)/misc.o: $(obj)/misc.c .config
+$(obj)/misc.o: $(obj)/misc.c .config FORCE
/usr/local/cris/gcc-cris -melf $(LINUXINCLUDE) -D__KERNEL__ -c $< -o $@
$(obj)/vmlinux: $(obj)/piggy.gz $(obj)/decompress.bin FORCE
$(call if_changed,image)
+ cat $(obj)/decompress_MCM.bin $(obj)/piggy.gz > $(obj)/vmlinux_MCM
+ cat $(obj)/decompress_416.bin $(obj)/piggy.gz > $(obj)/vmlinux_416
+ cat $(obj)/decompress_816.bin $(obj)/piggy.gz > $(obj)/vmlinux_816
+ cat $(obj)/decompress_832.bin $(obj)/piggy.gz > $(obj)/vmlinux_832
$(obj)/piggy.gz: $(obj)/../Image FORCE
$(call if_changed,gzip)
diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init.S
--- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init.S 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init.S 2007-05-28 16:42:15.000000000 +0200
@@ -0,0 +1,207 @@
+/* $Id: dram_init.S,v 1.5 2006/10/13 12:43:11 starvik Exp $
+ *
+ * DRAM/SDRAM initialization - alter with care
+ * This file is intended to be included from other assembler files
+ *
+ * Note: This file may not modify r9 because r9 is used to carry
+ * information from the decompresser to the kernel
+ *
+ * Copyright (C) 2000, 2001 Axis Communications AB
+ *
+ * Authors: Mikael Starvik (starvik@axis.com)
+ *
+ * $Log: dram_init.S,v $
+ * Revision 1.5 2006/10/13 12:43:11 starvik
+ * Merge of 2.6.18
+ *
+ * Revision 1.4 2003/09/22 09:21:59 starvik
+ * Decompresser is linked to 0x407xxxxx and sdram commands are at 0x000xxxxx
+ * so we need to mask off 12 bits.
+ *
+ * Revision 1.3 2003/03/31 09:38:37 starvik
+ * Corrected calculation of end of sdram init commands
+ *
+ * Revision 1.2 2002/11/19 13:33:29 starvik
+ * Changes from Linux 2.4
+ *
+ * Revision 1.13 2002/10/30 07:42:28 starvik
+ * Always read SDRAM command sequence from flash
+ *
+ * Revision 1.12 2002/08/09 11:37:37 orjanf
+ * Added double initialization work-around for Samsung SDRAMs.
+ *
+ * Revision 1.11 2002/06/04 11:43:21 starvik
+ * Check if mrs_data is specified in kernelconfig (necessary for MCM)
+ *
+ * Revision 1.10 2001/10/04 12:00:21 martinnn
+ * Added missing underscores.
+ *
+ * Revision 1.9 2001/10/01 14:47:35 bjornw
+ * Added register prefixes and removed underscores
+ *
+ * Revision 1.8 2001/05/15 07:12:45 hp
+ * Copy warning from head.S about r8 and r9
+ *
+ * Revision 1.7 2001/04/18 12:05:39 bjornw
+ * Fixed comments, and explicitely include config.h to be sure its there
+ *
+ * Revision 1.6 2001/04/10 06:20:16 starvik
+ * Delay should be 200us, not 200ns
+ *
+ * Revision 1.5 2001/04/09 06:01:13 starvik
+ * Added support for 100 MHz SDRAMs
+ *
+ * Revision 1.4 2001/03/26 14:24:01 bjornw
+ * Namechange of some config options
+ *
+ * Revision 1.3 2001/03/23 08:29:41 starvik
+ * Corrected calculation of mrs_data
+ *
+ * Revision 1.2 2001/02/08 15:20:00 starvik
+ * Corrected SDRAM initialization
+ * Should now be included as inline
+ *
+ * Revision 1.1 2001/01/29 13:08:02 starvik
+ * Initial version
+ * This file should be included from all assembler files that needs to
+ * initialize DRAM/SDRAM.
+ *
+ */
+
+/* Just to be certain the config file is included, we include it here
+ * explicitely instead of depending on it being included in the file that
+ * uses this code.
+ */
+
+
+ ;; WARNING! The registers r8 and r9 are used as parameters carrying
+ ;; information from the decompressor (if the kernel was compressed).
+ ;; They should not be used in the code below.
+
+#ifndef CONFIG_SVINTO_SIM
+ move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
+ move.d $r0, [R_WAITSTATES]
+
+ move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
+ move.d $r0, [R_BUS_CONFIG]
+
+#ifndef CONFIG_ETRAX_SDRAM
+ move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
+ move.d $r0, [R_DRAM_CONFIG]
+
+ move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
+ move.d $r0, [R_DRAM_TIMING]
+#else
+ ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
+ moveq 2, $r6
+_sdram_init:
+
+ ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
+
+ ; Bank configuration
+ move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0
+ move.d $r0, [R_SDRAM_CONFIG]
+
+ ; Calculate value of mrs_data
+ ; CAS latency = 2 && bus_width = 32 => 0x40
+ ; CAS latency = 3 && bus_width = 32 => 0x60
+ ; CAS latency = 2 && bus_width = 16 => 0x20
+ ; CAS latency = 3 && bus_width = 16 => 0x30
+
+ ; Check if value is already supplied in kernel config
+ move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r2
+ and.d 0x00ff0000, $r2
+ bne _set_timing
+ lsrq 16, $r2
+
+ move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
+ move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
+ move.d $r1, $r3
+ and.d 0x03, $r1 ; Get CAS latency
+ and.d 0x1000, $r3 ; 50 or 100 MHz?
+ beq _speed_50
+ nop
+_speed_100:
+ cmp.d 0x00, $r1 ; CAS latency = 2?
+ beq _bw_check
+ nop
+ or.d 0x20, $r2 ; CAS latency = 3
+ ba _bw_check
+ nop
+_speed_50:
+ cmp.d 0x01, $r1 ; CAS latency = 2?
+ beq _bw_check
+ nop
+ or.d 0x20, $r2 ; CAS latency = 3
+_bw_check:
+ move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1
+ and.d 0x800000, $r1 ; DRAM width is bit 23
+ bne _set_timing
+ nop
+ lsrq 1, $r2 ; 16 bits. Shift down value.
+
+ ; Set timing parameters. Starts master clock
+_set_timing:
+ move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
+ and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
+ or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
+ move.d $r1, $r5
+ or.d 0x0000c000, $r1 ; ref = disable
+ lslq 16, $r2 ; mrs data starts at bit 16
+ or.d $r2, $r1
+ move.d $r1, [R_SDRAM_TIMING]
+
+ ; Wait 200us
+ move.d 10000, $r2
+1: bne 1b
+ subq 1, $r2
+
+ ; Issue initialization command sequence
+ move.d _sdram_commands_start, $r2
+ and.d 0x000fffff, $r2 ; Make sure commands are read from flash
+ move.d _sdram_commands_end, $r3
+ and.d 0x000fffff, $r3
+1: clear.d $r4
+ move.b [$r2+], $r4
+ lslq 9, $r4 ; Command starts at bit 9
+ or.d $r1, $r4
+ move.d $r4, [R_SDRAM_TIMING]
+ nop ; Wait five nop cycles between each command
+ nop
+ nop
+ nop
+ nop
+ cmp.d $r2, $r3
+ bne 1b
+ nop
+ move.d $r5, [R_SDRAM_TIMING]
+ subq 1, $r6
+ bne _sdram_init
+ nop
+ ba _sdram_commands_end
+ nop
+
+_sdram_commands_start:
+ .byte 3 ; Precharge
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 1 ; mrs
+ .byte 0 ; nop
+_sdram_commands_end:
+#endif
+#endif
diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init_416.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init_416.S
--- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init_416.S 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init_416.S 2007-05-28 20:02:25.000000000 +0200
@@ -0,0 +1,207 @@
+/* $Id: dram_init.S,v 1.5 2006/10/13 12:43:11 starvik Exp $
+ *
+ * DRAM/SDRAM initialization - alter with care
+ * This file is intended to be included from other assembler files
+ *
+ * Note: This file may not modify r9 because r9 is used to carry
+ * information from the decompresser to the kernel
+ *
+ * Copyright (C) 2000, 2001 Axis Communications AB
+ *
+ * Authors: Mikael Starvik (starvik@axis.com)
+ *
+ * $Log: dram_init.S,v $
+ * Revision 1.5 2006/10/13 12:43:11 starvik
+ * Merge of 2.6.18
+ *
+ * Revision 1.4 2003/09/22 09:21:59 starvik
+ * Decompresser is linked to 0x407xxxxx and sdram commands are at 0x000xxxxx
+ * so we need to mask off 12 bits.
+ *
+ * Revision 1.3 2003/03/31 09:38:37 starvik
+ * Corrected calculation of end of sdram init commands
+ *
+ * Revision 1.2 2002/11/19 13:33:29 starvik
+ * Changes from Linux 2.4
+ *
+ * Revision 1.13 2002/10/30 07:42:28 starvik
+ * Always read SDRAM command sequence from flash
+ *
+ * Revision 1.12 2002/08/09 11:37:37 orjanf
+ * Added double initialization work-around for Samsung SDRAMs.
+ *
+ * Revision 1.11 2002/06/04 11:43:21 starvik
+ * Check if mrs_data is specified in kernelconfig (necessary for MCM)
+ *
+ * Revision 1.10 2001/10/04 12:00:21 martinnn
+ * Added missing underscores.
+ *
+ * Revision 1.9 2001/10/01 14:47:35 bjornw
+ * Added register prefixes and removed underscores
+ *
+ * Revision 1.8 2001/05/15 07:12:45 hp
+ * Copy warning from head.S about r8 and r9
+ *
+ * Revision 1.7 2001/04/18 12:05:39 bjornw
+ * Fixed comments, and explicitely include config.h to be sure its there
+ *
+ * Revision 1.6 2001/04/10 06:20:16 starvik
+ * Delay should be 200us, not 200ns
+ *
+ * Revision 1.5 2001/04/09 06:01:13 starvik
+ * Added support for 100 MHz SDRAMs
+ *
+ * Revision 1.4 2001/03/26 14:24:01 bjornw
+ * Namechange of some config options
+ *
+ * Revision 1.3 2001/03/23 08:29:41 starvik
+ * Corrected calculation of mrs_data
+ *
+ * Revision 1.2 2001/02/08 15:20:00 starvik
+ * Corrected SDRAM initialization
+ * Should now be included as inline
+ *
+ * Revision 1.1 2001/01/29 13:08:02 starvik
+ * Initial version
+ * This file should be included from all assembler files that needs to
+ * initialize DRAM/SDRAM.
+ *
+ */
+
+/* Just to be certain the config file is included, we include it here
+ * explicitely instead of depending on it being included in the file that
+ * uses this code.
+ */
+
+
+ ;; WARNING! The registers r8 and r9 are used as parameters carrying
+ ;; information from the decompressor (if the kernel was compressed).
+ ;; They should not be used in the code below.
+
+#ifndef CONFIG_SVINTO_SIM
+ move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
+ move.d $r0, [R_WAITSTATES]
+
+ move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
+ move.d $r0, [R_BUS_CONFIG]
+
+#ifndef CONFIG_ETRAX_SDRAM
+ move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
+ move.d $r0, [R_DRAM_CONFIG]
+
+ move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
+ move.d $r0, [R_DRAM_TIMING]
+#else
+ ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
+ moveq 2, $r6
+_sdram_init:
+
+ ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
+
+ ; Bank configuration
+ move.d 0x09603636, $r0
+ move.d $r0, [R_SDRAM_CONFIG]
+
+ ; Calculate value of mrs_data
+ ; CAS latency = 2 && bus_width = 32 => 0x40
+ ; CAS latency = 3 && bus_width = 32 => 0x60
+ ; CAS latency = 2 && bus_width = 16 => 0x20
+ ; CAS latency = 3 && bus_width = 16 => 0x30
+
+ ; Check if value is already supplied in kernel config
+ move.d 0x80008002, $r2
+ and.d 0x00ff0000, $r2
+ bne _set_timing
+ lsrq 16, $r2
+
+ move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
+ move.d 0x80008002, $r1
+ move.d $r1, $r3
+ and.d 0x03, $r1 ; Get CAS latency
+ and.d 0x1000, $r3 ; 50 or 100 MHz?
+ beq _speed_50
+ nop
+_speed_100:
+ cmp.d 0x00, $r1 ; CAS latency = 2?
+ beq _bw_check
+ nop
+ or.d 0x20, $r2 ; CAS latency = 3
+ ba _bw_check
+ nop
+_speed_50:
+ cmp.d 0x01, $r1 ; CAS latency = 2?
+ beq _bw_check
+ nop
+ or.d 0x20, $r2 ; CAS latency = 3
+_bw_check:
+ move.d 0x09603636, $r1
+ and.d 0x800000, $r1 ; DRAM width is bit 23
+ bne _set_timing
+ nop
+ lsrq 1, $r2 ; 16 bits. Shift down value.
+
+ ; Set timing parameters. Starts master clock
+_set_timing:
+ move.d 0x80008002, $r1
+ and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
+ or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
+ move.d $r1, $r5
+ or.d 0x0000c000, $r1 ; ref = disable
+ lslq 16, $r2 ; mrs data starts at bit 16
+ or.d $r2, $r1
+ move.d $r1, [R_SDRAM_TIMING]
+
+ ; Wait 200us
+ move.d 10000, $r2
+1: bne 1b
+ subq 1, $r2
+
+ ; Issue initialization command sequence
+ move.d _sdram_commands_start, $r2
+ and.d 0x000fffff, $r2 ; Make sure commands are read from flash
+ move.d _sdram_commands_end, $r3
+ and.d 0x000fffff, $r3
+1: clear.d $r4
+ move.b [$r2+], $r4
+ lslq 9, $r4 ; Command starts at bit 9
+ or.d $r1, $r4
+ move.d $r4, [R_SDRAM_TIMING]
+ nop ; Wait five nop cycles between each command
+ nop
+ nop
+ nop
+ nop
+ cmp.d $r2, $r3
+ bne 1b
+ nop
+ move.d $r5, [R_SDRAM_TIMING]
+ subq 1, $r6
+ bne _sdram_init
+ nop
+ ba _sdram_commands_end
+ nop
+
+_sdram_commands_start:
+ .byte 3 ; Precharge
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 1 ; mrs
+ .byte 0 ; nop
+_sdram_commands_end:
+#endif
+#endif
diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init_816.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init_816.S
--- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init_816.S 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init_816.S 2007-05-28 20:04:05.000000000 +0200
@@ -0,0 +1,207 @@
+/* $Id: dram_init.S,v 1.5 2006/10/13 12:43:11 starvik Exp $
+ *
+ * DRAM/SDRAM initialization - alter with care
+ * This file is intended to be included from other assembler files
+ *
+ * Note: This file may not modify r9 because r9 is used to carry
+ * information from the decompresser to the kernel
+ *
+ * Copyright (C) 2000, 2001 Axis Communications AB
+ *
+ * Authors: Mikael Starvik (starvik@axis.com)
+ *
+ * $Log: dram_init.S,v $
+ * Revision 1.5 2006/10/13 12:43:11 starvik
+ * Merge of 2.6.18
+ *
+ * Revision 1.4 2003/09/22 09:21:59 starvik
+ * Decompresser is linked to 0x407xxxxx and sdram commands are at 0x000xxxxx
+ * so we need to mask off 12 bits.
+ *
+ * Revision 1.3 2003/03/31 09:38:37 starvik
+ * Corrected calculation of end of sdram init commands
+ *
+ * Revision 1.2 2002/11/19 13:33:29 starvik
+ * Changes from Linux 2.4
+ *
+ * Revision 1.13 2002/10/30 07:42:28 starvik
+ * Always read SDRAM command sequence from flash
+ *
+ * Revision 1.12 2002/08/09 11:37:37 orjanf
+ * Added double initialization work-around for Samsung SDRAMs.
+ *
+ * Revision 1.11 2002/06/04 11:43:21 starvik
+ * Check if mrs_data is specified in kernelconfig (necessary for MCM)
+ *
+ * Revision 1.10 2001/10/04 12:00:21 martinnn
+ * Added missing underscores.
+ *
+ * Revision 1.9 2001/10/01 14:47:35 bjornw
+ * Added register prefixes and removed underscores
+ *
+ * Revision 1.8 2001/05/15 07:12:45 hp
+ * Copy warning from head.S about r8 and r9
+ *
+ * Revision 1.7 2001/04/18 12:05:39 bjornw
+ * Fixed comments, and explicitely include config.h to be sure its there
+ *
+ * Revision 1.6 2001/04/10 06:20:16 starvik
+ * Delay should be 200us, not 200ns
+ *
+ * Revision 1.5 2001/04/09 06:01:13 starvik
+ * Added support for 100 MHz SDRAMs
+ *
+ * Revision 1.4 2001/03/26 14:24:01 bjornw
+ * Namechange of some config options
+ *
+ * Revision 1.3 2001/03/23 08:29:41 starvik
+ * Corrected calculation of mrs_data
+ *
+ * Revision 1.2 2001/02/08 15:20:00 starvik
+ * Corrected SDRAM initialization
+ * Should now be included as inline
+ *
+ * Revision 1.1 2001/01/29 13:08:02 starvik
+ * Initial version
+ * This file should be included from all assembler files that needs to
+ * initialize DRAM/SDRAM.
+ *
+ */
+
+/* Just to be certain the config file is included, we include it here
+ * explicitely instead of depending on it being included in the file that
+ * uses this code.
+ */
+
+
+ ;; WARNING! The registers r8 and r9 are used as parameters carrying
+ ;; information from the decompressor (if the kernel was compressed).
+ ;; They should not be used in the code below.
+
+#ifndef CONFIG_SVINTO_SIM
+ move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
+ move.d $r0, [R_WAITSTATES]
+
+ move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
+ move.d $r0, [R_BUS_CONFIG]
+
+#ifndef CONFIG_ETRAX_SDRAM
+ move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
+ move.d $r0, [R_DRAM_CONFIG]
+
+ move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
+ move.d $r0, [R_DRAM_TIMING]
+#else
+ ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
+ moveq 2, $r6
+_sdram_init:
+
+ ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
+
+ ; Bank configuration
+ move.d 0x09603636, $r0
+ move.d $r0, [R_SDRAM_CONFIG]
+
+ ; Calculate value of mrs_data
+ ; CAS latency = 2 && bus_width = 32 => 0x40
+ ; CAS latency = 3 && bus_width = 32 => 0x60
+ ; CAS latency = 2 && bus_width = 16 => 0x20
+ ; CAS latency = 3 && bus_width = 16 => 0x30
+
+ ; Check if value is already supplied in kernel config
+ move.d 0x80008002, $r2
+ and.d 0x00ff0000, $r2
+ bne _set_timing
+ lsrq 16, $r2
+
+ move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
+ move.d 0x80008002, $r1
+ move.d $r1, $r3
+ and.d 0x03, $r1 ; Get CAS latency
+ and.d 0x1000, $r3 ; 50 or 100 MHz?
+ beq _speed_50
+ nop
+_speed_100:
+ cmp.d 0x00, $r1 ; CAS latency = 2?
+ beq _bw_check
+ nop
+ or.d 0x20, $r2 ; CAS latency = 3
+ ba _bw_check
+ nop
+_speed_50:
+ cmp.d 0x01, $r1 ; CAS latency = 2?
+ beq _bw_check
+ nop
+ or.d 0x20, $r2 ; CAS latency = 3
+_bw_check:
+ move.d 0x09603636, $r1
+ and.d 0x800000, $r1 ; DRAM width is bit 23
+ bne _set_timing
+ nop
+ lsrq 1, $r2 ; 16 bits. Shift down value.
+
+ ; Set timing parameters. Starts master clock
+_set_timing:
+ move.d 0x80008002, $r1
+ and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
+ or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
+ move.d $r1, $r5
+ or.d 0x0000c000, $r1 ; ref = disable
+ lslq 16, $r2 ; mrs data starts at bit 16
+ or.d $r2, $r1
+ move.d $r1, [R_SDRAM_TIMING]
+
+ ; Wait 200us
+ move.d 10000, $r2
+1: bne 1b
+ subq 1, $r2
+
+ ; Issue initialization command sequence
+ move.d _sdram_commands_start, $r2
+ and.d 0x000fffff, $r2 ; Make sure commands are read from flash
+ move.d _sdram_commands_end, $r3
+ and.d 0x000fffff, $r3
+1: clear.d $r4
+ move.b [$r2+], $r4
+ lslq 9, $r4 ; Command starts at bit 9
+ or.d $r1, $r4
+ move.d $r4, [R_SDRAM_TIMING]
+ nop ; Wait five nop cycles between each command
+ nop
+ nop
+ nop
+ nop
+ cmp.d $r2, $r3
+ bne 1b
+ nop
+ move.d $r5, [R_SDRAM_TIMING]
+ subq 1, $r6
+ bne _sdram_init
+ nop
+ ba _sdram_commands_end
+ nop
+
+_sdram_commands_start:
+ .byte 3 ; Precharge
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 1 ; mrs
+ .byte 0 ; nop
+_sdram_commands_end:
+#endif
+#endif
diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init_832.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init_832.S
--- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init_832.S 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init_832.S 2007-05-28 20:04:57.000000000 +0200
@@ -0,0 +1,207 @@
+/* $Id: dram_init.S,v 1.5 2006/10/13 12:43:11 starvik Exp $
+ *
+ * DRAM/SDRAM initialization - alter with care
+ * This file is intended to be included from other assembler files
+ *
+ * Note: This file may not modify r9 because r9 is used to carry
+ * information from the decompresser to the kernel
+ *
+ * Copyright (C) 2000, 2001 Axis Communications AB
+ *
+ * Authors: Mikael Starvik (starvik@axis.com)
+ *
+ * $Log: dram_init.S,v $
+ * Revision 1.5 2006/10/13 12:43:11 starvik
+ * Merge of 2.6.18
+ *
+ * Revision 1.4 2003/09/22 09:21:59 starvik
+ * Decompresser is linked to 0x407xxxxx and sdram commands are at 0x000xxxxx
+ * so we need to mask off 12 bits.
+ *
+ * Revision 1.3 2003/03/31 09:38:37 starvik
+ * Corrected calculation of end of sdram init commands
+ *
+ * Revision 1.2 2002/11/19 13:33:29 starvik
+ * Changes from Linux 2.4
+ *
+ * Revision 1.13 2002/10/30 07:42:28 starvik
+ * Always read SDRAM command sequence from flash
+ *
+ * Revision 1.12 2002/08/09 11:37:37 orjanf
+ * Added double initialization work-around for Samsung SDRAMs.
+ *
+ * Revision 1.11 2002/06/04 11:43:21 starvik
+ * Check if mrs_data is specified in kernelconfig (necessary for MCM)
+ *
+ * Revision 1.10 2001/10/04 12:00:21 martinnn
+ * Added missing underscores.
+ *
+ * Revision 1.9 2001/10/01 14:47:35 bjornw
+ * Added register prefixes and removed underscores
+ *
+ * Revision 1.8 2001/05/15 07:12:45 hp
+ * Copy warning from head.S about r8 and r9
+ *
+ * Revision 1.7 2001/04/18 12:05:39 bjornw
+ * Fixed comments, and explicitely include config.h to be sure its there
+ *
+ * Revision 1.6 2001/04/10 06:20:16 starvik
+ * Delay should be 200us, not 200ns
+ *
+ * Revision 1.5 2001/04/09 06:01:13 starvik
+ * Added support for 100 MHz SDRAMs
+ *
+ * Revision 1.4 2001/03/26 14:24:01 bjornw
+ * Namechange of some config options
+ *
+ * Revision 1.3 2001/03/23 08:29:41 starvik
+ * Corrected calculation of mrs_data
+ *
+ * Revision 1.2 2001/02/08 15:20:00 starvik
+ * Corrected SDRAM initialization
+ * Should now be included as inline
+ *
+ * Revision 1.1 2001/01/29 13:08:02 starvik
+ * Initial version
+ * This file should be included from all assembler files that needs to
+ * initialize DRAM/SDRAM.
+ *
+ */
+
+/* Just to be certain the config file is included, we include it here
+ * explicitely instead of depending on it being included in the file that
+ * uses this code.
+ */
+
+
+ ;; WARNING! The registers r8 and r9 are used as parameters carrying
+ ;; information from the decompressor (if the kernel was compressed).
+ ;; They should not be used in the code below.
+
+#ifndef CONFIG_SVINTO_SIM
+ move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
+ move.d $r0, [R_WAITSTATES]
+
+ move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
+ move.d $r0, [R_BUS_CONFIG]
+
+#ifndef CONFIG_ETRAX_SDRAM
+ move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
+ move.d $r0, [R_DRAM_CONFIG]
+
+ move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
+ move.d $r0, [R_DRAM_TIMING]
+#else
+ ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
+ moveq 2, $r6
+_sdram_init:
+
+ ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
+
+ ; Bank configuration
+ move.d 0x09603737, $r0
+ move.d $r0, [R_SDRAM_CONFIG]
+
+ ; Calculate value of mrs_data
+ ; CAS latency = 2 && bus_width = 32 => 0x40
+ ; CAS latency = 3 && bus_width = 32 => 0x60
+ ; CAS latency = 2 && bus_width = 16 => 0x20
+ ; CAS latency = 3 && bus_width = 16 => 0x30
+
+ ; Check if value is already supplied in kernel config
+ move.d 0x80008002, $r2
+ and.d 0x00ff0000, $r2
+ bne _set_timing
+ lsrq 16, $r2
+
+ move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
+ move.d 0x80008002, $r1
+ move.d $r1, $r3
+ and.d 0x03, $r1 ; Get CAS latency
+ and.d 0x1000, $r3 ; 50 or 100 MHz?
+ beq _speed_50
+ nop
+_speed_100:
+ cmp.d 0x00, $r1 ; CAS latency = 2?
+ beq _bw_check
+ nop
+ or.d 0x20, $r2 ; CAS latency = 3
+ ba _bw_check
+ nop
+_speed_50:
+ cmp.d 0x01, $r1 ; CAS latency = 2?
+ beq _bw_check
+ nop
+ or.d 0x20, $r2 ; CAS latency = 3
+_bw_check:
+ move.d 0x09603737, $r1
+ and.d 0x800000, $r1 ; DRAM width is bit 23
+ bne _set_timing
+ nop
+ lsrq 1, $r2 ; 16 bits. Shift down value.
+
+ ; Set timing parameters. Starts master clock
+_set_timing:
+ move.d 0x80008002, $r1
+ and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
+ or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
+ move.d $r1, $r5
+ or.d 0x0000c000, $r1 ; ref = disable
+ lslq 16, $r2 ; mrs data starts at bit 16
+ or.d $r2, $r1
+ move.d $r1, [R_SDRAM_TIMING]
+
+ ; Wait 200us
+ move.d 10000, $r2
+1: bne 1b
+ subq 1, $r2
+
+ ; Issue initialization command sequence
+ move.d _sdram_commands_start, $r2
+ and.d 0x000fffff, $r2 ; Make sure commands are read from flash
+ move.d _sdram_commands_end, $r3
+ and.d 0x000fffff, $r3
+1: clear.d $r4
+ move.b [$r2+], $r4
+ lslq 9, $r4 ; Command starts at bit 9
+ or.d $r1, $r4
+ move.d $r4, [R_SDRAM_TIMING]
+ nop ; Wait five nop cycles between each command
+ nop
+ nop
+ nop
+ nop
+ cmp.d $r2, $r3
+ bne 1b
+ nop
+ move.d $r5, [R_SDRAM_TIMING]
+ subq 1, $r6
+ bne _sdram_init
+ nop
+ ba _sdram_commands_end
+ nop
+
+_sdram_commands_start:
+ .byte 3 ; Precharge
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 1 ; mrs
+ .byte 0 ; nop
+_sdram_commands_end:
+#endif
+#endif
diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init_MCM.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init_MCM.S
--- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/dram_init_MCM.S 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/dram_init_MCM.S 2007-05-28 20:03:13.000000000 +0200
@@ -0,0 +1,207 @@
+/* $Id: dram_init.S,v 1.5 2006/10/13 12:43:11 starvik Exp $
+ *
+ * DRAM/SDRAM initialization - alter with care
+ * This file is intended to be included from other assembler files
+ *
+ * Note: This file may not modify r9 because r9 is used to carry
+ * information from the decompresser to the kernel
+ *
+ * Copyright (C) 2000, 2001 Axis Communications AB
+ *
+ * Authors: Mikael Starvik (starvik@axis.com)
+ *
+ * $Log: dram_init.S,v $
+ * Revision 1.5 2006/10/13 12:43:11 starvik
+ * Merge of 2.6.18
+ *
+ * Revision 1.4 2003/09/22 09:21:59 starvik
+ * Decompresser is linked to 0x407xxxxx and sdram commands are at 0x000xxxxx
+ * so we need to mask off 12 bits.
+ *
+ * Revision 1.3 2003/03/31 09:38:37 starvik
+ * Corrected calculation of end of sdram init commands
+ *
+ * Revision 1.2 2002/11/19 13:33:29 starvik
+ * Changes from Linux 2.4
+ *
+ * Revision 1.13 2002/10/30 07:42:28 starvik
+ * Always read SDRAM command sequence from flash
+ *
+ * Revision 1.12 2002/08/09 11:37:37 orjanf
+ * Added double initialization work-around for Samsung SDRAMs.
+ *
+ * Revision 1.11 2002/06/04 11:43:21 starvik
+ * Check if mrs_data is specified in kernelconfig (necessary for MCM)
+ *
+ * Revision 1.10 2001/10/04 12:00:21 martinnn
+ * Added missing underscores.
+ *
+ * Revision 1.9 2001/10/01 14:47:35 bjornw
+ * Added register prefixes and removed underscores
+ *
+ * Revision 1.8 2001/05/15 07:12:45 hp
+ * Copy warning from head.S about r8 and r9
+ *
+ * Revision 1.7 2001/04/18 12:05:39 bjornw
+ * Fixed comments, and explicitely include config.h to be sure its there
+ *
+ * Revision 1.6 2001/04/10 06:20:16 starvik
+ * Delay should be 200us, not 200ns
+ *
+ * Revision 1.5 2001/04/09 06:01:13 starvik
+ * Added support for 100 MHz SDRAMs
+ *
+ * Revision 1.4 2001/03/26 14:24:01 bjornw
+ * Namechange of some config options
+ *
+ * Revision 1.3 2001/03/23 08:29:41 starvik
+ * Corrected calculation of mrs_data
+ *
+ * Revision 1.2 2001/02/08 15:20:00 starvik
+ * Corrected SDRAM initialization
+ * Should now be included as inline
+ *
+ * Revision 1.1 2001/01/29 13:08:02 starvik
+ * Initial version
+ * This file should be included from all assembler files that needs to
+ * initialize DRAM/SDRAM.
+ *
+ */
+
+/* Just to be certain the config file is included, we include it here
+ * explicitely instead of depending on it being included in the file that
+ * uses this code.
+ */
+
+
+ ;; WARNING! The registers r8 and r9 are used as parameters carrying
+ ;; information from the decompressor (if the kernel was compressed).
+ ;; They should not be used in the code below.
+
+#ifndef CONFIG_SVINTO_SIM
+ move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
+ move.d $r0, [R_WAITSTATES]
+
+ move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
+ move.d $r0, [R_BUS_CONFIG]
+
+#ifndef CONFIG_ETRAX_SDRAM
+ move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
+ move.d $r0, [R_DRAM_CONFIG]
+
+ move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
+ move.d $r0, [R_DRAM_TIMING]
+#else
+ ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
+ moveq 2, $r6
+_sdram_init:
+
+ ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
+
+ ; Bank configuration
+ move.d 0x09603636, $r0
+ move.d $r0, [R_SDRAM_CONFIG]
+
+ ; Calculate value of mrs_data
+ ; CAS latency = 2 && bus_width = 32 => 0x40
+ ; CAS latency = 3 && bus_width = 32 => 0x60
+ ; CAS latency = 2 && bus_width = 16 => 0x20
+ ; CAS latency = 3 && bus_width = 16 => 0x30
+
+ ; Check if value is already supplied in kernel config
+ move.d 0x80608002, $r2
+ and.d 0x00ff0000, $r2
+ bne _set_timing
+ lsrq 16, $r2
+
+ move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
+ move.d 0x80608002, $r1
+ move.d $r1, $r3
+ and.d 0x03, $r1 ; Get CAS latency
+ and.d 0x1000, $r3 ; 50 or 100 MHz?
+ beq _speed_50
+ nop
+_speed_100:
+ cmp.d 0x00, $r1 ; CAS latency = 2?
+ beq _bw_check
+ nop
+ or.d 0x20, $r2 ; CAS latency = 3
+ ba _bw_check
+ nop
+_speed_50:
+ cmp.d 0x01, $r1 ; CAS latency = 2?
+ beq _bw_check
+ nop
+ or.d 0x20, $r2 ; CAS latency = 3
+_bw_check:
+ move.d 0x09603636, $r1
+ and.d 0x800000, $r1 ; DRAM width is bit 23
+ bne _set_timing
+ nop
+ lsrq 1, $r2 ; 16 bits. Shift down value.
+
+ ; Set timing parameters. Starts master clock
+_set_timing:
+ move.d 0x80608002, $r1
+ and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
+ or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
+ move.d $r1, $r5
+ or.d 0x0000c000, $r1 ; ref = disable
+ lslq 16, $r2 ; mrs data starts at bit 16
+ or.d $r2, $r1
+ move.d $r1, [R_SDRAM_TIMING]
+
+ ; Wait 200us
+ move.d 10000, $r2
+1: bne 1b
+ subq 1, $r2
+
+ ; Issue initialization command sequence
+ move.d _sdram_commands_start, $r2
+ and.d 0x000fffff, $r2 ; Make sure commands are read from flash
+ move.d _sdram_commands_end, $r3
+ and.d 0x000fffff, $r3
+1: clear.d $r4
+ move.b [$r2+], $r4
+ lslq 9, $r4 ; Command starts at bit 9
+ or.d $r1, $r4
+ move.d $r4, [R_SDRAM_TIMING]
+ nop ; Wait five nop cycles between each command
+ nop
+ nop
+ nop
+ nop
+ cmp.d $r2, $r3
+ bne 1b
+ nop
+ move.d $r5, [R_SDRAM_TIMING]
+ subq 1, $r6
+ bne _sdram_init
+ nop
+ ba _sdram_commands_end
+ nop
+
+_sdram_commands_start:
+ .byte 3 ; Precharge
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 2 ; refresh
+ .byte 0 ; nop
+ .byte 1 ; mrs
+ .byte 0 ; nop
+_sdram_commands_end:
+#endif
+#endif
diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/head_416.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/head_416.S
--- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/head_416.S 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/head_416.S 2007-05-28 17:16:28.000000000 +0200
@@ -0,0 +1,126 @@
+/*
+ * arch/cris/boot/compressed/head.S
+ *
+ * Copyright (C) 1999, 2001 Axis Communications AB
+ *
+ * Code that sets up the DRAM registers, calls the
+ * decompressor to unpack the piggybacked kernel, and jumps.
+ *
+ */
+
+#define ASSEMBLER_MACROS_ONLY
+#include <asm/arch/sv_addr_ag.h>
+
+#define RAM_INIT_MAGIC 0x56902387
+#define COMMAND_LINE_MAGIC 0x87109563
+
+ ;; Exported symbols
+
+ .globl _input_data
+
+
+ .text
+
+ nop
+ di
+
+;; We need to initialze DRAM registers before we start using the DRAM
+
+ cmp.d RAM_INIT_MAGIC, r8 ; Already initialized?
+ beq dram_init_finished
+ nop
+
+#include "dram_init_416.S"
+
+dram_init_finished:
+
+ ;; Initiate the PA and PB ports
+
+ move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, r0
+ move.b r0, [R_PORT_PA_DATA]
+
+ move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, r0
+ move.b r0, [R_PORT_PA_DIR]
+
+ move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, r0
+ move.b r0, [R_PORT_PB_DATA]
+
+ move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, r0
+ move.b r0, [R_PORT_PB_DIR]
+
+ ;; Setup the stack to a suitably high address.
+ ;; We assume 8 MB is the minimum DRAM in an eLinux
+ ;; product and put the sp at the top for now.
+
+ move.d 0x40800000, sp
+
+ ;; Figure out where the compressed piggyback image is
+ ;; in the flash (since we wont try to copy it to DRAM
+ ;; before unpacking). It is at _edata, but in flash.
+ ;; Use (_edata - basse) as offset to the current PC.
+
+basse: move.d pc, r5
+ and.d 0x7fffffff, r5 ; strip any non-cache bit
+ subq 2, r5 ; compensate for the move.d pc instr
+ move.d r5, r0 ; save for later - flash address of 'basse'
+ add.d _edata, r5
+ sub.d basse, r5 ; r5 = flash address of '_edata'
+
+ ;; Copy text+data to DRAM
+
+ move.d basse, r1 ; destination
+ move.d _edata, r2 ; end destination
+1: move.w [r0+], r3
+ move.w r3, [r1+]
+ cmp.d r2, r1
+ bcs 1b
+ nop
+
+ move.d r5, [_input_data] ; for the decompressor
+
+
+ ;; Clear the decompressors BSS (between _edata and _end)
+
+ moveq 0, r0
+ move.d _edata, r1
+ move.d _end, r2
+1: move.w r0, [r1+]
+ cmp.d r2, r1
+ bcs 1b
+ nop
+
+ ;; Save command line magic and address.
+ move.d _cmd_line_magic, $r12
+ move.d $r10, [$r12]
+ move.d _cmd_line_addr, $r12
+ move.d $r11, [$r12]
+
+ ;; Do the decompression and save compressed size in _inptr
+
+ jsr _decompress_kernel
+
+ ;; Put start address of root partition in r9 so the kernel can use it
+ ;; when mounting from flash
+
+ move.d [_input_data], r9 ; flash address of compressed kernel
+ add.d [_inptr], r9 ; size of compressed kernel
+
+ ;; Restore command line magic and address.
+ move.d _cmd_line_magic, $r10
+ move.d [$r10], $r10
+ move.d _cmd_line_addr, $r11
+ move.d [$r11], $r11
+
+ ;; Enter the decompressed kernel
+ move.d RAM_INIT_MAGIC, r8 ; Tell kernel that DRAM is initialized
+ jump 0x40004000 ; kernel is linked to this address
+
+ .data
+
+_input_data:
+ .dword 0 ; used by the decompressor
+_cmd_line_magic:
+ .dword 0
+_cmd_line_addr:
+ .dword 0
+#include "hw_settings_416.S"
diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/head_816.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/head_816.S
--- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/head_816.S 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/head_816.S 2007-05-28 17:16:58.000000000 +0200
@@ -0,0 +1,126 @@
+/*
+ * arch/cris/boot/compressed/head.S
+ *
+ * Copyright (C) 1999, 2001 Axis Communications AB
+ *
+ * Code that sets up the DRAM registers, calls the
+ * decompressor to unpack the piggybacked kernel, and jumps.
+ *
+ */
+
+#define ASSEMBLER_MACROS_ONLY
+#include <asm/arch/sv_addr_ag.h>
+
+#define RAM_INIT_MAGIC 0x56902387
+#define COMMAND_LINE_MAGIC 0x87109563
+
+ ;; Exported symbols
+
+ .globl _input_data
+
+
+ .text
+
+ nop
+ di
+
+;; We need to initialze DRAM registers before we start using the DRAM
+
+ cmp.d RAM_INIT_MAGIC, r8 ; Already initialized?
+ beq dram_init_finished
+ nop
+
+#include "dram_init_816.S"
+
+dram_init_finished:
+
+ ;; Initiate the PA and PB ports
+
+ move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, r0
+ move.b r0, [R_PORT_PA_DATA]
+
+ move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, r0
+ move.b r0, [R_PORT_PA_DIR]
+
+ move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, r0
+ move.b r0, [R_PORT_PB_DATA]
+
+ move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, r0
+ move.b r0, [R_PORT_PB_DIR]
+
+ ;; Setup the stack to a suitably high address.
+ ;; We assume 8 MB is the minimum DRAM in an eLinux
+ ;; product and put the sp at the top for now.
+
+ move.d 0x40800000, sp
+
+ ;; Figure out where the compressed piggyback image is
+ ;; in the flash (since we wont try to copy it to DRAM
+ ;; before unpacking). It is at _edata, but in flash.
+ ;; Use (_edata - basse) as offset to the current PC.
+
+basse: move.d pc, r5
+ and.d 0x7fffffff, r5 ; strip any non-cache bit
+ subq 2, r5 ; compensate for the move.d pc instr
+ move.d r5, r0 ; save for later - flash address of 'basse'
+ add.d _edata, r5
+ sub.d basse, r5 ; r5 = flash address of '_edata'
+
+ ;; Copy text+data to DRAM
+
+ move.d basse, r1 ; destination
+ move.d _edata, r2 ; end destination
+1: move.w [r0+], r3
+ move.w r3, [r1+]
+ cmp.d r2, r1
+ bcs 1b
+ nop
+
+ move.d r5, [_input_data] ; for the decompressor
+
+
+ ;; Clear the decompressors BSS (between _edata and _end)
+
+ moveq 0, r0
+ move.d _edata, r1
+ move.d _end, r2
+1: move.w r0, [r1+]
+ cmp.d r2, r1
+ bcs 1b
+ nop
+
+ ;; Save command line magic and address.
+ move.d _cmd_line_magic, $r12
+ move.d $r10, [$r12]
+ move.d _cmd_line_addr, $r12
+ move.d $r11, [$r12]
+
+ ;; Do the decompression and save compressed size in _inptr
+
+ jsr _decompress_kernel
+
+ ;; Put start address of root partition in r9 so the kernel can use it
+ ;; when mounting from flash
+
+ move.d [_input_data], r9 ; flash address of compressed kernel
+ add.d [_inptr], r9 ; size of compressed kernel
+
+ ;; Restore command line magic and address.
+ move.d _cmd_line_magic, $r10
+ move.d [$r10], $r10
+ move.d _cmd_line_addr, $r11
+ move.d [$r11], $r11
+
+ ;; Enter the decompressed kernel
+ move.d RAM_INIT_MAGIC, r8 ; Tell kernel that DRAM is initialized
+ jump 0x40004000 ; kernel is linked to this address
+
+ .data
+
+_input_data:
+ .dword 0 ; used by the decompressor
+_cmd_line_magic:
+ .dword 0
+_cmd_line_addr:
+ .dword 0
+#include "hw_settings_816.S"
diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/head_832.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/head_832.S
--- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/head_832.S 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/head_832.S 2007-05-28 17:17:12.000000000 +0200
@@ -0,0 +1,126 @@
+/*
+ * arch/cris/boot/compressed/head.S
+ *
+ * Copyright (C) 1999, 2001 Axis Communications AB
+ *
+ * Code that sets up the DRAM registers, calls the
+ * decompressor to unpack the piggybacked kernel, and jumps.
+ *
+ */
+
+#define ASSEMBLER_MACROS_ONLY
+#include <asm/arch/sv_addr_ag.h>
+
+#define RAM_INIT_MAGIC 0x56902387
+#define COMMAND_LINE_MAGIC 0x87109563
+
+ ;; Exported symbols
+
+ .globl _input_data
+
+
+ .text
+
+ nop
+ di
+
+;; We need to initialze DRAM registers before we start using the DRAM
+
+ cmp.d RAM_INIT_MAGIC, r8 ; Already initialized?
+ beq dram_init_finished
+ nop
+
+#include "dram_init_832.S"
+
+dram_init_finished:
+
+ ;; Initiate the PA and PB ports
+
+ move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, r0
+ move.b r0, [R_PORT_PA_DATA]
+
+ move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, r0
+ move.b r0, [R_PORT_PA_DIR]
+
+ move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, r0
+ move.b r0, [R_PORT_PB_DATA]
+
+ move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, r0
+ move.b r0, [R_PORT_PB_DIR]
+
+ ;; Setup the stack to a suitably high address.
+ ;; We assume 8 MB is the minimum DRAM in an eLinux
+ ;; product and put the sp at the top for now.
+
+ move.d 0x40800000, sp
+
+ ;; Figure out where the compressed piggyback image is
+ ;; in the flash (since we wont try to copy it to DRAM
+ ;; before unpacking). It is at _edata, but in flash.
+ ;; Use (_edata - basse) as offset to the current PC.
+
+basse: move.d pc, r5
+ and.d 0x7fffffff, r5 ; strip any non-cache bit
+ subq 2, r5 ; compensate for the move.d pc instr
+ move.d r5, r0 ; save for later - flash address of 'basse'
+ add.d _edata, r5
+ sub.d basse, r5 ; r5 = flash address of '_edata'
+
+ ;; Copy text+data to DRAM
+
+ move.d basse, r1 ; destination
+ move.d _edata, r2 ; end destination
+1: move.w [r0+], r3
+ move.w r3, [r1+]
+ cmp.d r2, r1
+ bcs 1b
+ nop
+
+ move.d r5, [_input_data] ; for the decompressor
+
+
+ ;; Clear the decompressors BSS (between _edata and _end)
+
+ moveq 0, r0
+ move.d _edata, r1
+ move.d _end, r2
+1: move.w r0, [r1+]
+ cmp.d r2, r1
+ bcs 1b
+ nop
+
+ ;; Save command line magic and address.
+ move.d _cmd_line_magic, $r12
+ move.d $r10, [$r12]
+ move.d _cmd_line_addr, $r12
+ move.d $r11, [$r12]
+
+ ;; Do the decompression and save compressed size in _inptr
+
+ jsr _decompress_kernel
+
+ ;; Put start address of root partition in r9 so the kernel can use it
+ ;; when mounting from flash
+
+ move.d [_input_data], r9 ; flash address of compressed kernel
+ add.d [_inptr], r9 ; size of compressed kernel
+
+ ;; Restore command line magic and address.
+ move.d _cmd_line_magic, $r10
+ move.d [$r10], $r10
+ move.d _cmd_line_addr, $r11
+ move.d [$r11], $r11
+
+ ;; Enter the decompressed kernel
+ move.d RAM_INIT_MAGIC, r8 ; Tell kernel that DRAM is initialized
+ jump 0x40004000 ; kernel is linked to this address
+
+ .data
+
+_input_data:
+ .dword 0 ; used by the decompressor
+_cmd_line_magic:
+ .dword 0
+_cmd_line_addr:
+ .dword 0
+#include "hw_settings_832.S"
diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/head_MCM.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/head_MCM.S
--- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/head_MCM.S 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/head_MCM.S 2007-05-28 17:17:51.000000000 +0200
@@ -0,0 +1,126 @@
+/*
+ * arch/cris/boot/compressed/head.S
+ *
+ * Copyright (C) 1999, 2001 Axis Communications AB
+ *
+ * Code that sets up the DRAM registers, calls the
+ * decompressor to unpack the piggybacked kernel, and jumps.
+ *
+ */
+
+#define ASSEMBLER_MACROS_ONLY
+#include <asm/arch/sv_addr_ag.h>
+
+#define RAM_INIT_MAGIC 0x56902387
+#define COMMAND_LINE_MAGIC 0x87109563
+
+ ;; Exported symbols
+
+ .globl _input_data
+
+
+ .text
+
+ nop
+ di
+
+;; We need to initialze DRAM registers before we start using the DRAM
+
+ cmp.d RAM_INIT_MAGIC, r8 ; Already initialized?
+ beq dram_init_finished
+ nop
+
+#include "dram_init_MCM.S"
+
+dram_init_finished:
+
+ ;; Initiate the PA and PB ports
+
+ move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, r0
+ move.b r0, [R_PORT_PA_DATA]
+
+ move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, r0
+ move.b r0, [R_PORT_PA_DIR]
+
+ move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, r0
+ move.b r0, [R_PORT_PB_DATA]
+
+ move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, r0
+ move.b r0, [R_PORT_PB_DIR]
+
+ ;; Setup the stack to a suitably high address.
+ ;; We assume 8 MB is the minimum DRAM in an eLinux
+ ;; product and put the sp at the top for now.
+
+ move.d 0x40800000, sp
+
+ ;; Figure out where the compressed piggyback image is
+ ;; in the flash (since we wont try to copy it to DRAM
+ ;; before unpacking). It is at _edata, but in flash.
+ ;; Use (_edata - basse) as offset to the current PC.
+
+basse: move.d pc, r5
+ and.d 0x7fffffff, r5 ; strip any non-cache bit
+ subq 2, r5 ; compensate for the move.d pc instr
+ move.d r5, r0 ; save for later - flash address of 'basse'
+ add.d _edata, r5
+ sub.d basse, r5 ; r5 = flash address of '_edata'
+
+ ;; Copy text+data to DRAM
+
+ move.d basse, r1 ; destination
+ move.d _edata, r2 ; end destination
+1: move.w [r0+], r3
+ move.w r3, [r1+]
+ cmp.d r2, r1
+ bcs 1b
+ nop
+
+ move.d r5, [_input_data] ; for the decompressor
+
+
+ ;; Clear the decompressors BSS (between _edata and _end)
+
+ moveq 0, r0
+ move.d _edata, r1
+ move.d _end, r2
+1: move.w r0, [r1+]
+ cmp.d r2, r1
+ bcs 1b
+ nop
+
+ ;; Save command line magic and address.
+ move.d _cmd_line_magic, $r12
+ move.d $r10, [$r12]
+ move.d _cmd_line_addr, $r12
+ move.d $r11, [$r12]
+
+ ;; Do the decompression and save compressed size in _inptr
+
+ jsr _decompress_kernel
+
+ ;; Put start address of root partition in r9 so the kernel can use it
+ ;; when mounting from flash
+
+ move.d [_input_data], r9 ; flash address of compressed kernel
+ add.d [_inptr], r9 ; size of compressed kernel
+
+ ;; Restore command line magic and address.
+ move.d _cmd_line_magic, $r10
+ move.d [$r10], $r10
+ move.d _cmd_line_addr, $r11
+ move.d [$r11], $r11
+
+ ;; Enter the decompressed kernel
+ move.d RAM_INIT_MAGIC, r8 ; Tell kernel that DRAM is initialized
+ jump 0x40004000 ; kernel is linked to this address
+
+ .data
+
+_input_data:
+ .dword 0 ; used by the decompressor
+_cmd_line_magic:
+ .dword 0
+_cmd_line_addr:
+ .dword 0
+#include "hw_settings_MCM.S"
diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings.S
--- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings.S 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings.S 2007-05-28 17:14:14.000000000 +0200
@@ -0,0 +1,62 @@
+/*
+ * $Id: hw_settings.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $
+ *
+ * This table is used by some tools to extract hardware parameters.
+ * The table should be included in the kernel and the decompressor.
+ * Don't forget to update the tools if you change this table.
+ *
+ * Copyright (C) 2001 Axis Communications AB
+ *
+ * Authors: Mikael Starvik (starvik@axis.com)
+ */
+
+#define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \
+ (CONFIG_ETRAX_DEF_R_PORT_PA_DATA))
+#define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \
+ (CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \
+ (CONFIG_ETRAX_DEF_R_PORT_PB_DATA))
+
+ .ascii "HW_PARAM_MAGIC" ; Magic number
+ .dword 0xc0004000 ; Kernel start address
+
+ ; Debug port
+#ifdef CONFIG_ETRAX_DEBUG_PORT0
+ .dword 0
+#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
+ .dword 1
+#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
+ .dword 2
+#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
+ .dword 3
+#else
+ .dword 4 ; No debug
+#endif
+
+ ; SDRAM or EDO DRAM?
+#ifdef CONFIG_ETRAX_SDRAM
+ .dword 1
+#else
+ .dword 0
+#endif
+
+ ; Register values
+ .dword R_WAITSTATES
+ .dword CONFIG_ETRAX_DEF_R_WAITSTATES
+ .dword R_BUS_CONFIG
+ .dword CONFIG_ETRAX_DEF_R_BUS_CONFIG
+#ifdef CONFIG_ETRAX_SDRAM
+ .dword R_SDRAM_CONFIG
+ .dword CONFIG_ETRAX_DEF_R_SDRAM_CONFIG
+ .dword R_SDRAM_TIMING
+ .dword CONFIG_ETRAX_DEF_R_SDRAM_TIMING
+#else
+ .dword R_DRAM_CONFIG
+ .dword CONFIG_ETRAX_DEF_R_DRAM_CONFIG
+ .dword R_DRAM_TIMING
+ .dword CONFIG_ETRAX_DEF_R_DRAM_TIMING
+#endif
+ .dword R_PORT_PA_SET
+ .dword PA_SET_VALUE
+ .dword R_PORT_PB_SET
+ .dword PB_SET_VALUE
+ .dword 0 ; No more register values
diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings_416.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings_416.S
--- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings_416.S 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings_416.S 2007-05-28 20:12:02.000000000 +0200
@@ -0,0 +1,62 @@
+/*
+ * $Id: hw_settings.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $
+ *
+ * This table is used by some tools to extract hardware parameters.
+ * The table should be included in the kernel and the decompressor.
+ * Don't forget to update the tools if you change this table.
+ *
+ * Copyright (C) 2001 Axis Communications AB
+ *
+ * Authors: Mikael Starvik (starvik@axis.com)
+ */
+
+#define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \
+ (CONFIG_ETRAX_DEF_R_PORT_PA_DATA))
+#define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \
+ (CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \
+ (CONFIG_ETRAX_DEF_R_PORT_PB_DATA))
+
+ .ascii "HW_PARAM_MAGIC" ; Magic number
+ .dword 0xc0004000 ; Kernel start address
+
+ ; Debug port
+#ifdef CONFIG_ETRAX_DEBUG_PORT0
+ .dword 0
+#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
+ .dword 1
+#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
+ .dword 2
+#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
+ .dword 3
+#else
+ .dword 4 ; No debug
+#endif
+
+ ; SDRAM or EDO DRAM?
+#ifdef CONFIG_ETRAX_SDRAM
+ .dword 1
+#else
+ .dword 0
+#endif
+
+ ; Register values
+ .dword R_WAITSTATES
+ .dword CONFIG_ETRAX_DEF_R_WAITSTATES
+ .dword R_BUS_CONFIG
+ .dword CONFIG_ETRAX_DEF_R_BUS_CONFIG
+#ifdef CONFIG_ETRAX_SDRAM
+ .dword R_SDRAM_CONFIG
+ .dword 0x09603636
+ .dword R_SDRAM_TIMING
+ .dword 0x80008002
+#else
+ .dword R_DRAM_CONFIG
+ .dword CONFIG_ETRAX_DEF_R_DRAM_CONFIG
+ .dword R_DRAM_TIMING
+ .dword CONFIG_ETRAX_DEF_R_DRAM_TIMING
+#endif
+ .dword R_PORT_PA_SET
+ .dword PA_SET_VALUE
+ .dword R_PORT_PB_SET
+ .dword PB_SET_VALUE
+ .dword 0 ; No more register values
diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings_816.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings_816.S
--- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings_816.S 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings_816.S 2007-05-28 20:12:29.000000000 +0200
@@ -0,0 +1,62 @@
+/*
+ * $Id: hw_settings.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $
+ *
+ * This table is used by some tools to extract hardware parameters.
+ * The table should be included in the kernel and the decompressor.
+ * Don't forget to update the tools if you change this table.
+ *
+ * Copyright (C) 2001 Axis Communications AB
+ *
+ * Authors: Mikael Starvik (starvik@axis.com)
+ */
+
+#define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \
+ (CONFIG_ETRAX_DEF_R_PORT_PA_DATA))
+#define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \
+ (CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \
+ (CONFIG_ETRAX_DEF_R_PORT_PB_DATA))
+
+ .ascii "HW_PARAM_MAGIC" ; Magic number
+ .dword 0xc0004000 ; Kernel start address
+
+ ; Debug port
+#ifdef CONFIG_ETRAX_DEBUG_PORT0
+ .dword 0
+#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
+ .dword 1
+#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
+ .dword 2
+#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
+ .dword 3
+#else
+ .dword 4 ; No debug
+#endif
+
+ ; SDRAM or EDO DRAM?
+#ifdef CONFIG_ETRAX_SDRAM
+ .dword 1
+#else
+ .dword 0
+#endif
+
+ ; Register values
+ .dword R_WAITSTATES
+ .dword CONFIG_ETRAX_DEF_R_WAITSTATES
+ .dword R_BUS_CONFIG
+ .dword CONFIG_ETRAX_DEF_R_BUS_CONFIG
+#ifdef CONFIG_ETRAX_SDRAM
+ .dword R_SDRAM_CONFIG
+ .dword 0x09603636
+ .dword R_SDRAM_TIMING
+ .dword 0x80008002
+#else
+ .dword R_DRAM_CONFIG
+ .dword CONFIG_ETRAX_DEF_R_DRAM_CONFIG
+ .dword R_DRAM_TIMING
+ .dword CONFIG_ETRAX_DEF_R_DRAM_TIMING
+#endif
+ .dword R_PORT_PA_SET
+ .dword PA_SET_VALUE
+ .dword R_PORT_PB_SET
+ .dword PB_SET_VALUE
+ .dword 0 ; No more register values
diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings_832.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings_832.S
--- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings_832.S 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings_832.S 2007-05-28 20:12:55.000000000 +0200
@@ -0,0 +1,62 @@
+/*
+ * $Id: hw_settings.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $
+ *
+ * This table is used by some tools to extract hardware parameters.
+ * The table should be included in the kernel and the decompressor.
+ * Don't forget to update the tools if you change this table.
+ *
+ * Copyright (C) 2001 Axis Communications AB
+ *
+ * Authors: Mikael Starvik (starvik@axis.com)
+ */
+
+#define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \
+ (CONFIG_ETRAX_DEF_R_PORT_PA_DATA))
+#define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \
+ (CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \
+ (CONFIG_ETRAX_DEF_R_PORT_PB_DATA))
+
+ .ascii "HW_PARAM_MAGIC" ; Magic number
+ .dword 0xc0004000 ; Kernel start address
+
+ ; Debug port
+#ifdef CONFIG_ETRAX_DEBUG_PORT0
+ .dword 0
+#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
+ .dword 1
+#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
+ .dword 2
+#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
+ .dword 3
+#else
+ .dword 4 ; No debug
+#endif
+
+ ; SDRAM or EDO DRAM?
+#ifdef CONFIG_ETRAX_SDRAM
+ .dword 1
+#else
+ .dword 0
+#endif
+
+ ; Register values
+ .dword R_WAITSTATES
+ .dword CONFIG_ETRAX_DEF_R_WAITSTATES
+ .dword R_BUS_CONFIG
+ .dword CONFIG_ETRAX_DEF_R_BUS_CONFIG
+#ifdef CONFIG_ETRAX_SDRAM
+ .dword R_SDRAM_CONFIG
+ .dword CONFIG_ETRAX_DEF_R_SDRAM_CONFIG
+ .dword R_SDRAM_TIMING
+ .dword CONFIG_ETRAX_DEF_R_SDRAM_TIMING
+#else
+ .dword R_DRAM_CONFIG
+ .dword 0x09603737
+ .dword R_DRAM_TIMING
+ .dword 0x80008002
+#endif
+ .dword R_PORT_PA_SET
+ .dword PA_SET_VALUE
+ .dword R_PORT_PB_SET
+ .dword PB_SET_VALUE
+ .dword 0 ; No more register values
diff -urN linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings_MCM.S linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings_MCM.S
--- linux-2.6.19.2.orig/arch/cris/arch-v10/boot/compressed/hw_settings_MCM.S 1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.19.2/arch/cris/arch-v10/boot/compressed/hw_settings_MCM.S 2007-05-28 20:11:31.000000000 +0200
@@ -0,0 +1,62 @@
+/*
+ * $Id: hw_settings.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $
+ *
+ * This table is used by some tools to extract hardware parameters.
+ * The table should be included in the kernel and the decompressor.
+ * Don't forget to update the tools if you change this table.
+ *
+ * Copyright (C) 2001 Axis Communications AB
+ *
+ * Authors: Mikael Starvik (starvik@axis.com)
+ */
+
+#define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \
+ (CONFIG_ETRAX_DEF_R_PORT_PA_DATA))
+#define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \
+ (CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \
+ (CONFIG_ETRAX_DEF_R_PORT_PB_DATA))
+
+ .ascii "HW_PARAM_MAGIC" ; Magic number
+ .dword 0xc0004000 ; Kernel start address
+
+ ; Debug port
+#ifdef CONFIG_ETRAX_DEBUG_PORT0
+ .dword 0
+#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
+ .dword 1
+#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
+ .dword 2
+#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
+ .dword 3
+#else
+ .dword 4 ; No debug
+#endif
+
+ ; SDRAM or EDO DRAM?
+#ifdef CONFIG_ETRAX_SDRAM
+ .dword 1
+#else
+ .dword 0
+#endif
+
+ ; Register values
+ .dword R_WAITSTATES
+ .dword CONFIG_ETRAX_DEF_R_WAITSTATES
+ .dword R_BUS_CONFIG
+ .dword CONFIG_ETRAX_DEF_R_BUS_CONFIG
+#ifdef CONFIG_ETRAX_SDRAM
+ .dword R_SDRAM_CONFIG
+ .dword 0x09603636
+ .dword R_SDRAM_TIMING
+ .dword 0x80608002
+#else
+ .dword R_DRAM_CONFIG
+ .dword CONFIG_ETRAX_DEF_R_DRAM_CONFIG
+ .dword R_DRAM_TIMING
+ .dword CONFIG_ETRAX_DEF_R_DRAM_TIMING
+#endif
+ .dword R_PORT_PA_SET
+ .dword PA_SET_VALUE
+ .dword R_PORT_PB_SET
+ .dword PB_SET_VALUE
+ .dword 0 ; No more register values
Copy Permalink