mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-18 14:21:53 +02:00
129 lines
4.1 KiB
Diff
129 lines
4.1 KiB
Diff
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--- a/arch/mips/bcm63xx/dev-spi.c
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+++ b/arch/mips/bcm63xx/dev-spi.c
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@@ -106,11 +106,15 @@ int __init bcm63xx_spi_register(void)
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if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
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spi_resources[0].end += BCM_6338_RSET_SPI_SIZE - 1;
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spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE;
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+ spi_pdata.msg_type_shift = SPI_6338_MSG_TYPE_SHIFT;
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+ spi_pdata.msg_ctl_width = SPI_6338_MSG_CTL_WIDTH;
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}
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if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
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spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
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spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
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+ spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
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+ spi_pdata.msg_ctl_width = SPI_6358_MSG_CTL_WIDTH;
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}
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bcm63xx_spi_regs_init();
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
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@@ -9,6 +9,8 @@ int __init bcm63xx_spi_register(void);
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struct bcm63xx_spi_pdata {
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unsigned int fifo_size;
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+ unsigned int msg_type_shift;
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+ unsigned int msg_ctl_width;
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int bus_num;
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int num_chipselect;
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u32 speed_hz;
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -987,7 +987,8 @@
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#define SPI_6338_FILL_BYTE 0x07
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#define SPI_6338_MSG_TAIL 0x09
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#define SPI_6338_RX_TAIL 0x0b
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-#define SPI_6338_MSG_CTL 0x40
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+#define SPI_6338_MSG_CTL 0x40 /* 8-bits register */
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+#define SPI_6338_MSG_CTL_WIDTH 8
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#define SPI_6338_MSG_DATA 0x41
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#define SPI_6338_MSG_DATA_SIZE 0x3f
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#define SPI_6338_RX_DATA 0x80
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@@ -1003,7 +1004,8 @@
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#define SPI_6348_FILL_BYTE 0x07
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#define SPI_6348_MSG_TAIL 0x09
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#define SPI_6348_RX_TAIL 0x0b
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-#define SPI_6348_MSG_CTL 0x40
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+#define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
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+#define SPI_6348_MSG_CTL_WIDTH 8
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#define SPI_6348_MSG_DATA 0x41
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#define SPI_6348_MSG_DATA_SIZE 0x3f
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#define SPI_6348_RX_DATA 0x80
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@@ -1011,6 +1013,7 @@
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/* BCM 6358 SPI core */
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#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
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+#define SPI_6358_MSG_CTL_WIDTH 16
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#define SPI_6358_MSG_DATA 0x02
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#define SPI_6358_MSG_DATA_SIZE 0x21e
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#define SPI_6358_RX_DATA 0x400
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@@ -1027,6 +1030,7 @@
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/* BCM 6358 SPI core */
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#define SPI_6368_MSG_CTL 0x00 /* 16-bits register */
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+#define SPI_6368_MSG_CTL_WIDTH 16
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#define SPI_6368_MSG_DATA 0x02
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#define SPI_6368_MSG_DATA_SIZE 0x21e
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#define SPI_6368_RX_DATA 0x400
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@@ -1048,7 +1052,10 @@
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#define SPI_HD_W 0x01
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#define SPI_HD_R 0x02
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#define SPI_BYTE_CNT_SHIFT 0
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-#define SPI_MSG_TYPE_SHIFT 14
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+#define SPI_6338_MSG_TYPE_SHIFT 6
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+#define SPI_6348_MSG_TYPE_SHIFT 6
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+#define SPI_6358_MSG_TYPE_SHIFT 14
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+#define SPI_6368_MSG_TYPE_SHIFT 14
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/* Command */
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#define SPI_CMD_NOOP 0x00
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--- a/drivers/spi/spi-bcm63xx.c
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+++ b/drivers/spi/spi-bcm63xx.c
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@@ -47,6 +47,8 @@ struct bcm63xx_spi {
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/* Platform data */
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u32 speed_hz;
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unsigned fifo_size;
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+ unsigned int msg_type_shift;
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+ unsigned int msg_ctl_width;
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/* Data buffers */
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const unsigned char *tx_ptr;
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@@ -221,13 +223,24 @@ static unsigned int bcm63xx_txrx_bufs(st
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msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
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if (t->rx_buf && t->tx_buf)
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- msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
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+ msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
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else if (t->rx_buf)
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- msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
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+ msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
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else if (t->tx_buf)
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- msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
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+ msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
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- bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
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+ switch (bs->msg_ctl_width) {
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+ case 8:
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+ bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
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+ break;
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+ case 16:
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+ bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
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+ break;
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+ default:
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+ dev_err(&spi->dev, "unknown MSG_CTL width: %d\n",
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+ bs->msg_ctl_width);
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+ return 0;
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+ }
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/* Issue the transfer */
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cmd = SPI_CMD_START_IMMEDIATE;
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@@ -406,6 +419,8 @@ static int __devinit bcm63xx_spi_probe(s
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master->transfer_one_message = bcm63xx_spi_transfer_one;
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master->mode_bits = MODEBITS;
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bs->speed_hz = pdata->speed_hz;
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+ bs->msg_type_shift = pdata->msg_type_shift;
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+ bs->msg_ctl_width = pdata->msg_ctl_width;
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bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
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bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
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