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254 lines
5.5 KiB
C
254 lines
5.5 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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* Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_regs.h>
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#include <bcm63xx_io.h>
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#include <bcm63xx_irq.h>
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/*
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* dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
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* prioritize any interrupt relatively to another. the static counter
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* will resume the loop where it ended the last time we left this
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* function.
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*/
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static void bcm63xx_irq_dispatch_internal(void)
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{
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u32 pending;
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static int i;
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pending = bcm_perf_readl(PERF_IRQMASK_REG) &
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bcm_perf_readl(PERF_IRQSTAT_REG);
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if (!pending)
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return ;
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while (1) {
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int to_call = i;
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i = (i + 1) & 0x1f;
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if (pending & (1 << to_call)) {
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do_IRQ(to_call + IRQ_INTERNAL_BASE);
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break;
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}
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}
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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u32 cause;
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do {
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cause = read_c0_cause() & read_c0_status() & ST0_IM;
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if (!cause)
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break;
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if (cause & CAUSEF_IP7)
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do_IRQ(7);
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if (cause & CAUSEF_IP2)
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bcm63xx_irq_dispatch_internal();
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if (cause & CAUSEF_IP3)
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do_IRQ(IRQ_EXT_0);
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if (cause & CAUSEF_IP4)
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do_IRQ(IRQ_EXT_1);
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if (cause & CAUSEF_IP5)
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do_IRQ(IRQ_EXT_2);
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if (cause & CAUSEF_IP6)
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do_IRQ(IRQ_EXT_3);
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} while (1);
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}
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/*
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* internal IRQs operations: only mask/unmask on PERF irq mask
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* register.
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*/
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static inline void bcm63xx_internal_irq_mask(unsigned int irq)
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{
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u32 mask;
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irq -= IRQ_INTERNAL_BASE;
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mask = bcm_perf_readl(PERF_IRQMASK_REG);
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mask &= ~(1 << irq);
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bcm_perf_writel(mask, PERF_IRQMASK_REG);
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}
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static void bcm63xx_internal_irq_unmask(unsigned int irq)
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{
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u32 mask;
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irq -= IRQ_INTERNAL_BASE;
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mask = bcm_perf_readl(PERF_IRQMASK_REG);
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mask |= (1 << irq);
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bcm_perf_writel(mask, PERF_IRQMASK_REG);
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}
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static unsigned int bcm63xx_internal_irq_startup(unsigned int irq)
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{
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bcm63xx_internal_irq_unmask(irq);
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return 0;
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}
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/*
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* external IRQs operations: mask/unmask and clear on PERF external
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* irq control register.
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*/
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static void bcm63xx_external_irq_mask(unsigned int irq)
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{
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u32 reg;
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irq -= IRQ_EXT_BASE;
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reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
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reg &= ~EXTIRQ_CFG_MASK(irq);
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bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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}
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static void bcm63xx_external_irq_unmask(unsigned int irq)
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{
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u32 reg;
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irq -= IRQ_EXT_BASE;
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reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
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reg |= EXTIRQ_CFG_MASK(irq);
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bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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}
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static void bcm63xx_external_irq_clear(unsigned int irq)
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{
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u32 reg;
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irq -= IRQ_EXT_BASE;
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reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
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reg |= EXTIRQ_CFG_CLEAR(irq);
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bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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}
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static unsigned int bcm63xx_external_irq_startup(unsigned int irq)
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{
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set_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
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irq_enable_hazard();
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bcm63xx_external_irq_unmask(irq);
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return 0;
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}
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static void bcm63xx_external_irq_shutdown(unsigned int irq)
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{
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bcm63xx_external_irq_mask(irq);
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clear_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
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irq_disable_hazard();
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}
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static int bcm63xx_external_irq_set_type(unsigned int irq,
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unsigned int flow_type)
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{
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u32 reg;
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struct irq_desc *desc = irq_desc + irq;
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irq -= IRQ_EXT_BASE;
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flow_type &= IRQ_TYPE_SENSE_MASK;
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if (flow_type == IRQ_TYPE_NONE)
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flow_type = IRQ_TYPE_LEVEL_LOW;
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reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
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switch (flow_type) {
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case IRQ_TYPE_EDGE_BOTH:
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reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
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reg |= EXTIRQ_CFG_BOTHEDGE(irq);
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break;
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case IRQ_TYPE_EDGE_RISING:
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reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
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reg |= EXTIRQ_CFG_SENSE(irq);
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reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
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reg &= ~EXTIRQ_CFG_SENSE(irq);
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reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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reg |= EXTIRQ_CFG_LEVELSENSE(irq);
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reg |= EXTIRQ_CFG_SENSE(irq);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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reg |= EXTIRQ_CFG_LEVELSENSE(irq);
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reg &= ~EXTIRQ_CFG_SENSE(irq);
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break;
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default:
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printk(KERN_ERR "bogus flow type combination given !\n");
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return -EINVAL;
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}
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bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
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desc->status |= IRQ_LEVEL;
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desc->handle_irq = handle_level_irq;
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} else {
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desc->handle_irq = handle_edge_irq;
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}
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return 0;
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}
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static struct irq_chip bcm63xx_internal_irq_chip = {
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.name = "bcm63xx_ipic",
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.startup = bcm63xx_internal_irq_startup,
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.shutdown = bcm63xx_internal_irq_mask,
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.mask = bcm63xx_internal_irq_mask,
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.mask_ack = bcm63xx_internal_irq_mask,
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.unmask = bcm63xx_internal_irq_unmask,
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};
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static struct irq_chip bcm63xx_external_irq_chip = {
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.name = "bcm63xx_epic",
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.startup = bcm63xx_external_irq_startup,
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.shutdown = bcm63xx_external_irq_shutdown,
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.ack = bcm63xx_external_irq_clear,
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.mask = bcm63xx_external_irq_mask,
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.unmask = bcm63xx_external_irq_unmask,
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.set_type = bcm63xx_external_irq_set_type,
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};
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static struct irqaction cpu_ip2_cascade_action = {
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.handler = no_action,
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.name = "cascade_ip2",
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};
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void __init arch_init_irq(void)
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{
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int i;
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mips_cpu_irq_init();
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for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
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set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip,
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handle_level_irq);
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for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
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set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip,
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handle_edge_irq);
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setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
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}
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