mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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87 lines
2.5 KiB
Diff
87 lines
2.5 KiB
Diff
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From 9d9e4d955b1def6d63470bcf45e8ead1b2ae4892 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Sat, 4 Aug 2012 15:03:56 +0000
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Subject: [PATCH] MIPS: ath79: add USB platform setup code for AR934X
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commit 00ffed582fe8a3f7556593c0e8baaf3da3df85b0 upstream.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/4172/
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Conflicts:
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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---
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arch/mips/ath79/dev-usb.c | 28 ++++++++++++++++++++++++
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 7 ++++++
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2 files changed, 35 insertions(+)
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--- a/arch/mips/ath79/dev-usb.c
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+++ b/arch/mips/ath79/dev-usb.c
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@@ -193,6 +193,32 @@ static void __init ar933x_usb_setup(void
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platform_device_register(&ath79_ehci_device);
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}
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+static void __init ar934x_usb_setup(void)
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+{
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+ u32 bootstrap;
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+
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+ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
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+ if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
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+ return;
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+
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+ ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE);
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+ udelay(1000);
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+
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+ ath79_device_reset_clear(AR934X_RESET_USB_PHY);
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+ udelay(1000);
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+
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+ ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG);
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+ udelay(1000);
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+
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+ ath79_device_reset_clear(AR934X_RESET_USB_HOST);
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+ udelay(1000);
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+
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+ ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE,
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+ AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
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+ ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
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+ platform_device_register(&ath79_ehci_device);
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+}
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+
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void __init ath79_register_usb(void)
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{
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if (soc_is_ar71xx())
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@@ -205,6 +231,8 @@ void __init ath79_register_usb(void)
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ar913x_usb_setup();
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else if (soc_is_ar933x())
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ar933x_usb_setup();
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+ else if (soc_is_ar934x())
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+ ar934x_usb_setup();
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else
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BUG();
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}
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -65,6 +65,8 @@
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#define AR934X_WMAC_SIZE 0x20000
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#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
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#define AR934X_SRIF_SIZE 0x1000
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+#define AR934X_EHCI_BASE 0x1b000000
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+#define AR934X_EHCI_SIZE 0x200
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/*
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* DDR_CTRL block
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@@ -290,6 +292,11 @@
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#define AR933X_RESET_USB_PHY BIT(4)
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#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
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+#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
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+#define AR934X_RESET_USB_HOST BIT(5)
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+#define AR934X_RESET_USB_PHY BIT(4)
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+#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
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+
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#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
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#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
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