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git://projects.qi-hardware.com/openwrt-xburst.git
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43 lines
1.2 KiB
Diff
43 lines
1.2 KiB
Diff
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From 03de60e7fd96c0d78d293dc859a2a9ad2d2f16c4 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 3 Aug 2012 10:22:41 +0200
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Subject: [PATCH 03/25] svip hack
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---
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arch/mips/kernel/cevt-r4k.c | 2 ++
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arch/mips/mm/c-r4k.c | 3 +++
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2 files changed, 5 insertions(+), 0 deletions(-)
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diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
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index 51095dd..db9070c 100644
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--- a/arch/mips/kernel/cevt-r4k.c
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+++ b/arch/mips/kernel/cevt-r4k.c
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@@ -171,8 +171,10 @@ int __cpuinit r4k_clockevent_init(void)
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if (!cpu_has_counter || !mips_hpt_frequency)
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return -ENXIO;
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+#ifndef CONFIG_SOC_SVIP
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if (!c0_compare_int_usable())
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return -ENXIO;
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+#endif
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/*
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* With vectored interrupts things are getting platform specific.
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diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
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index 4f9eb0b..de3475e 100644
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--- a/arch/mips/mm/c-r4k.c
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+++ b/arch/mips/mm/c-r4k.c
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@@ -1252,6 +1252,9 @@ static void __cpuinit setup_scache(void)
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way_string[c->scache.ways], c->scache.linesz);
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}
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#else
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+#ifdef CONFIG_SOC_SVIP
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+ return;
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+#endif
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if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
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panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
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#endif
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--
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1.7.9.1
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