mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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381 lines
16 KiB
C
381 lines
16 KiB
C
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/*
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* m5485pci.h -- ColdFire 547x/548x PCI controller support.
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* Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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#ifndef __MCF548X_PCI_H__
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#define __MCF548X_PCI_H__
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/* PCI Type 0 Configuration Registers */
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#define MCF_PCIIDR MCF_REG32(0x000B00)
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/* PCI Device ID/Vendor ID */
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#define MCF_PCISCR MCF_REG32(0x000B04)
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/* PCI Status/Command */
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#define MCF_PCICCRIR MCF_REG32(0x000B08)
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/* PCI Class Code / Revision ID */
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#define MCF_PCICR1 MCF_REG32(0x000B0C)
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/* PCI Configuration 1 Register */
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#define MCF_PCIBAR0 MCF_REG32(0x000B10)
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/* PCI Base Address Register 0 */
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#define MCF_PCIBAR1 MCF_REG32(0x000B14)
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/* PCI Base Address Register 1 */
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#define MCF_PCICCPR MCF_REG32(0x000B28)
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/* PCI Cardbus CIS Pointer */
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#define MCF_PCISID MCF_REG32(0x000B2C)
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/* Subsystem ID/Subsystem Vendor ID*/
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#define MCF_PCIERBAR MCF_REG32(0x000B30)
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/* PCI Expansion ROM */
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#define MCF_PCICPR MCF_REG32(0x000B30)
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/* PCI Capabilities Pointer */
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#define MCF_PCICR2 MCF_REG32(0x000B3C)
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/* PCI Configuration Register 2 */
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/* General Control/Status Registers */
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#define MCF_PCIGSCR MCF_REG32(0x000B60)
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/* Global Status/Control Register */
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#define MCF_PCITBATR0 MCF_REG32(0x000B64)
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/* Target Base Address Translation 0*/
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#define MCF_PCITBATR1 MCF_REG32(0x000B68)
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/* Target Base Address Translation 1*/
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#define MCF_PCITCR MCF_REG32(0x000B6C)
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/* Target Control Register */
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#define MCF_PCIIW0BTAR MCF_REG32(0x000B70)
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/* Initiator Window 0 Base Address */
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#define MCF_PCIIW1BTAR MCF_REG32(0x000B74)
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/* Initiator Window 1 Base Address */
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#define MCF_PCIIW2BTAR MCF_REG32(0x000B78)
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/* Initiator Window 2 Base Address */
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#define MCF_PCIIWCR MCF_REG32(0x000B80)
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/* Initiator Window Configuration */
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#define MCF_PCIICR MCF_REG32(0x000B84)
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/* Initiator Control Register */
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#define MCF_PCIISR MCF_REG32(0x000B88)
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/* Initiator Status Register */
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#define MCF_PCICAR MCF_REG32(0x000BF8)
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/* Configuration Address Register */
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/* CommBus FIFO Transmit Interface Registers */
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#define MCF_PCITPSR MCF_REG32(0x008400)
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/* Tx Packet Size Register */
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#define MCF_PCITSAR MCF_REG32(0x008404)
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/* Tx Start Address Register */
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#define MCF_PCITTCR MCF_REG32(0x008408)
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/* Tx Transaction Control Register */
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#define MCF_PCITER MCF_REG32(0x00840C)
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/* Tx Enables Register */
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#define MCF_PCITNAR MCF_REG32(0x008410)
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/* Tx Next Address Register */
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#define MCF_PCITLWR MCF_REG32(0x008414)
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/* Tx Last Word Register */
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#define MCF_PCITDCR MCF_REG32(0x008418)
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/* Tx Done Counts Register */
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#define MCF_PCITSR MCF_REG32(0x00841C)
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/* Tx Status Register */
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#define MCF_PCITFDR MCF_REG32(0x008440)
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/* Tx FIFO Data Register */
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#define MCF_PCITFSR MCF_REG32(0x008444)
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/* Tx FIFO Status Register */
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#define MCF_PCITFCR MCF_REG32(0x008448)
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/* Tx FIFO Control Register */
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#define MCF_PCITFAR MCF_REG32(0x00844C)
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/* Tx FIFO Alarm Register */
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#define MCF_PCITFRPR MCF_REG32(0x008450)
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/* Tx FIFO Read Pointer Register */
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#define MCF_PCITFWPR MCF_REG32(0x008454)
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/* Tx FIFO Write Pointer Register */
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/* CommBus FIFO Receive Interface Registers */
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#define MCF_PCIRPSR MCF_REG32(0x008480)
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/* Tx Packet Size Register */
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#define MCF_PCIRSAR MCF_REG32(0x008484)
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/* Tx Start Address Register */
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#define MCF_PCIRTCR MCF_REG32(0x008488)
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/* Tx Transaction Control Register */
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#define MCF_PCIRER MCF_REG32(0x00848C)
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/* Tx Enables Register */
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#define MCF_PCIRNAR MCF_REG32(0x008490)
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/* Tx Next Address Register */
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#define MCF_PCIRDCR MCF_REG32(0x008498)
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/* Tx Done Counts Register */
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#define MCF_PCIRSR MCF_REG32(0x00849C)
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/* Tx Status Register */
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#define MCF_PCIRFDR MCF_REG32(0x0084C0)
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/* Tx FIFO Data Register */
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#define MCF_PCIRFSR MCF_REG32(0x0084C4)
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/* Tx FIFO Status Register */
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#define MCF_PCIRFCR MCF_REG32(0x0084C8)
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/* Tx FIFO Control Register */
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#define MCF_PCIRFAR MCF_REG32(0x0084CC)
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/* Tx FIFO Alarm Register */
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#define MCF_PCIRFRPR MCF_REG32(0x0084D0)
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/* Tx FIFO Read Pointer Register */
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#define MCF_PCIRFWPR MCF_REG32(0x0084D4)
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/* Tx FIFO Write Pointer Register */
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/* PCI Arbiter Registers */
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#define MCF_PCIARB_PACR MCF_REG32(0x000C00)
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#define MCF_PCIARB_PASR MCF_REG32(0x000C04)
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/* Bit definitions and macros for MCF_PCIIDR */
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#define MCF_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)<<0)
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#define MCF_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for MCF_PCISCR */
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#define MCF_PCISCR_M (0x00000002)
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#define MCF_PCISCR_B (0x00000004)
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#define MCF_PCISCR_SP (0x00000008)
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#define MCF_PCISCR_MW (0x00000010)
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#define MCF_PCISCR_PER (0x00000040)
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#define MCF_PCISCR_S (0x00000100)
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#define MCF_PCISCR_F (0x00000200)
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#define MCF_PCISCR_C (0x00100000)
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#define MCF_PCISCR_66M (0x00200000)
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#define MCF_PCISCR_R (0x00400000)
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#define MCF_PCISCR_FC (0x00800000)
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#define MCF_PCISCR_DP (0x01000000)
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#define MCF_PCISCR_DT(x) (((x)&0x00000003)<<25)
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#define MCF_PCISCR_TS (0x08000000)
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#define MCF_PCISCR_TR (0x10000000)
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#define MCF_PCISCR_MA (0x20000000)
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#define MCF_PCISCR_SE (0x40000000)
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#define MCF_PCISCR_PE (0x80000000)
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/* Bit definitions and macros for MCF_PCICCRIR */
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#define MCF_PCICCRIR_REVID(x) (((x)&0x000000FF)<<0)
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#define MCF_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8)
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/* Bit definitions and macros for MCF_PCICR1 */
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#define MCF_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)<<0)
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#define MCF_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8)
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#define MCF_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16)
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#define MCF_PCICR1_BIST(x) (((x)&0x000000FF)<<24)
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/* Bit definitions and macros for MCF_PCIBAR# */
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#define MCF_PCIBAR0_ADDR(x) (((x)&0x00003FFF)<<18)
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#define MCF_PCIBAR1_ADDR(x) (((x)&0x00000003)<<30)
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/* Bit definitions and macros for MCF_PCICR2 */
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#define MCF_PCICR2_INTLINE(x) (((x)&0x000000FF)<<0)
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#define MCF_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8)
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#define MCF_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16)
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#define MCF_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24)
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/* Bit definitions and macros for MCF_PCIGSCR */
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#define MCF_PCIGSCR_PR (0x00000001)
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#define MCF_PCIGSCR_SEE (0x00001000)
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#define MCF_PCIGSCR_PEE (0x00002000)
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#define MCF_PCIGSCR_SE (0x10000000)
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#define MCF_PCIGSCR_PE (0x20000000)
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/* Bit definitions and macros for MCF_PCITBATR0 */
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#define MCF_PCITBATR0_EN (0x00000001)
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#define MCF_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18)
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/* Bit definitions and macros for MCF_PCITBATR1 */
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#define MCF_PCITBATR1_EN (0x00000001)
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#define MCF_PCITBATR1_BAT1(x) (((x)&0x00000003)<<30)
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/* Bit definitions and macros for MCF_PCITCR */
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#define MCF_PCITCR_P (0x00010000)
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#define MCF_PCITCR_LD (0x01000000)
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/* Bit definitions and macros for MCF_PCIIW0BTAR */
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#define MCF_PCIIW0BTAR_WTA0(x) (((x)&0x000000FF)<<8)
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#define MCF_PCIIW0BTAR_WAM0(x) (((x)&0x000000FF)<<16)
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#define MCF_PCIIW0BTAR_WBA0(x) (((x)&0x000000FF)<<24)
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/* Bit definitions and macros for MCF_PCIIW1BTAR */
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#define MCF_PCIIW1BTAR_WTA1(x) (((x)&0x000000FF)<<8)
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#define MCF_PCIIW1BTAR_WAM1(x) (((x)&0x000000FF)<<16)
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#define MCF_PCIIW1BTAR_WBA1(x) (((x)&0x000000FF)<<24)
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/* Bit definitions and macros for MCF_PCIIW2BTAR */
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#define MCF_PCIIW2BTAR_WTA2(x) (((x)&0x000000FF)<<8)
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#define MCF_PCIIW2BTAR_WAM2(x) (((x)&0x000000FF)<<16)
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#define MCF_PCIIW2BTAR_WBA2(x) (((x)&0x000000FF)<<24)
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/* Bit definitions and macros for MCF_PCIIWCR */
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#define MCF_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8)
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#define MCF_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16)
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#define MCF_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24)
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#define MCF_PCIIWCR_WINCTRL0_MEMREAD (0x01000000)
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#define MCF_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000)
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#define MCF_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000)
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#define MCF_PCIIWCR_WINCTRL0_IO (0x09000000)
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#define MCF_PCIIWCR_WINCTRL0_E (0x01000000)
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#define MCF_PCIIWCR_WINCTRL1_MEMREAD (0x00010000)
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#define MCF_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000)
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#define MCF_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000)
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#define MCF_PCIIWCR_WINCTRL1_IO (0x00090000)
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#define MCF_PCIIWCR_WINCTRL1_E (0x00010000)
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#define MCF_PCIIWCR_WINCTRL2_MEMREAD (0x00000100)
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#define MCF_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300)
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#define MCF_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500)
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#define MCF_PCIIWCR_WINCTRL2_IO (0x00000900)
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#define MCF_PCIIWCR_WINCTRL2_E (0x00000100)
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/* Bit definitions and macros for MCF_PCIICR */
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#define MCF_PCIICR_MAXRETRY(x) (((x)&0x000000FF)<<0)
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#define MCF_PCIICR_TAE (0x01000000)
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#define MCF_PCIICR_IAE (0x02000000)
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#define MCF_PCIICR_REE (0x04000000)
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/* Bit definitions and macros for MCF_PCIISR */
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#define MCF_PCIISR_TA (0x01000000)
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#define MCF_PCIISR_IA (0x02000000)
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#define MCF_PCIISR_RE (0x04000000)
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/* Bit definitions and macros for MCF_PCICAR */
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#define MCF_PCICAR_DWORD(x) (((x)&0x0000003F)<<2)
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#define MCF_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8)
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#define MCF_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11)
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#define MCF_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16)
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#define MCF_PCICAR_E (0x80000000)
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/* Bit definitions and macros for MCF_PCITPSR */
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#define MCF_PCITPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for MCF_PCITTCR */
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#define MCF_PCITTCR_DI (0x00000001)
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#define MCF_PCITTCR_W (0x00000010)
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#define MCF_PCITTCR_MAXBEATS(x) (((x)&0x00000007)<<8)
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#define MCF_PCITTCR_MAXRETRY(x) (((x)&0x000000FF)<<16)
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#define MCF_PCITTCR_PCICMD(x) (((x)&0x0000000F)<<24)
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/* Bit definitions and macros for MCF_PCITER */
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#define MCF_PCITER_NE (0x00010000)
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#define MCF_PCITER_IAE (0x00020000)
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#define MCF_PCITER_TAE (0x00040000)
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#define MCF_PCITER_RE (0x00080000)
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#define MCF_PCITER_SE (0x00100000)
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#define MCF_PCITER_FEE (0x00200000)
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#define MCF_PCITER_ME (0x01000000)
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#define MCF_PCITER_BE (0x08000000)
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#define MCF_PCITER_CM (0x10000000)
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#define MCF_PCITER_RF (0x40000000)
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#define MCF_PCITER_RC (0x80000000)
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/* Bit definitions and macros for MCF_PCITDCR */
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#define MCF_PCITDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0)
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#define MCF_PCITDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for MCF_PCITSR */
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#define MCF_PCITSR_IA (0x00010000)
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#define MCF_PCITSR_TA (0x00020000)
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#define MCF_PCITSR_RE (0x00040000)
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#define MCF_PCITSR_SE (0x00080000)
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#define MCF_PCITSR_FE (0x00100000)
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#define MCF_PCITSR_BE1 (0x00200000)
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#define MCF_PCITSR_BE2 (0x00400000)
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#define MCF_PCITSR_BE3 (0x00800000)
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#define MCF_PCITSR_NT (0x01000000)
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/* Bit definitions and macros for MCF_PCITFSR */
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#define MCF_PCITFSR_EMT (0x00010000)
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#define MCF_PCITFSR_ALARM (0x00020000)
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#define MCF_PCITFSR_FU (0x00040000)
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#define MCF_PCITFSR_FR (0x00080000)
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#define MCF_PCITFSR_OF (0x00100000)
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#define MCF_PCITFSR_UF (0x00200000)
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#define MCF_PCITFSR_RXW (0x00400000)
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/* Bit definitions and macros for MCF_PCITFCR */
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#define MCF_PCITFCR_OF_MSK (0x00080000)
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#define MCF_PCITFCR_UF_MSK (0x00100000)
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#define MCF_PCITFCR_RXW_MSK (0x00200000)
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#define MCF_PCITFCR_FAE_MSK (0x00400000)
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#define MCF_PCITFCR_IP_MSK (0x00800000)
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#define MCF_PCITFCR_GR(x) (((x)&0x00000007)<<24)
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/* Bit definitions and macros for MCF_PCITFAR */
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#define MCF_PCITFAR_ALARM(x) (((x)&0x0000007F)<<0)
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/* Bit definitions and macros for MCF_PCITFRPR */
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#define MCF_PCITFRPR_READ(x) (((x)&0x00000FFF)<<0)
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/* Bit definitions and macros for MCF_PCITFWPR */
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#define MCF_PCITFWPR_WRITE(x) (((x)&0x00000FFF)<<0)
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/* Bit definitions and macros for MCF_PCIRPSR */
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#define MCF_PCIRPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for MCF_PCIRTCR */
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#define MCF_PCIRTCR_DI (0x00000001)
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#define MCF_PCIRTCR_W (0x00000010)
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#define MCF_PCIRTCR_MAXBEATS(x) (((x)&0x00000007)<<8)
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#define MCF_PCIRTCR_FB (0x00001000)
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#define MCF_PCIRTCR_MAXRETRY(x) (((x)&0x000000FF)<<16)
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#define MCF_PCIRTCR_PCICMD(x) (((x)&0x0000000F)<<24)
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/* Bit definitions and macros for MCF_PCIRER */
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#define MCF_PCIRER_NE (0x00010000)
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#define MCF_PCIRER_IAE (0x00020000)
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#define MCF_PCIRER_TAE (0x00040000)
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#define MCF_PCIRER_RE (0x00080000)
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#define MCF_PCIRER_SE (0x00100000)
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#define MCF_PCIRER_FEE (0x00200000)
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#define MCF_PCIRER_ME (0x01000000)
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#define MCF_PCIRER_BE (0x08000000)
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#define MCF_PCIRER_CM (0x10000000)
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#define MCF_PCIRER_FE (0x20000000)
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#define MCF_PCIRER_RF (0x40000000)
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#define MCF_PCIRER_RC (0x80000000)
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/* Bit definitions and macros for MCF_PCIRDCR */
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#define MCF_PCIRDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0)
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||
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#define MCF_PCIRDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16)
|
||
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|
||
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/* Bit definitions and macros for MCF_PCIRSR */
|
||
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#define MCF_PCIRSR_IA (0x00010000)
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||
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#define MCF_PCIRSR_TA (0x00020000)
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||
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#define MCF_PCIRSR_RE (0x00040000)
|
||
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#define MCF_PCIRSR_SE (0x00080000)
|
||
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|
#define MCF_PCIRSR_FE (0x00100000)
|
||
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|
#define MCF_PCIRSR_BE1 (0x00200000)
|
||
|
|
#define MCF_PCIRSR_BE2 (0x00400000)
|
||
|
|
#define MCF_PCIRSR_BE3 (0x00800000)
|
||
|
|
#define MCF_PCIRSR_NT (0x01000000)
|
||
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|
|
||
|
|
/* Bit definitions and macros for MCF_PCIRFSR */
|
||
|
|
#define MCF_PCIRFSR_EMT (0x00010000)
|
||
|
|
#define MCF_PCIRFSR_ALARM (0x00020000)
|
||
|
|
#define MCF_PCIRFSR_FU (0x00040000)
|
||
|
|
#define MCF_PCIRFSR_FR (0x00080000)
|
||
|
|
#define MCF_PCIRFSR_OF (0x00100000)
|
||
|
|
#define MCF_PCIRFSR_UF (0x00200000)
|
||
|
|
#define MCF_PCIRFSR_RXW (0x00400000)
|
||
|
|
|
||
|
|
/* Bit definitions and macros for MCF_PCIRFCR */
|
||
|
|
#define MCF_PCIRFCR_OF_MSK (0x00080000)
|
||
|
|
#define MCF_PCIRFCR_UF_MSK (0x00100000)
|
||
|
|
#define MCF_PCIRFCR_RXW_MSK (0x00200000)
|
||
|
|
#define MCF_PCIRFCR_FAE_MSK (0x00400000)
|
||
|
|
#define MCF_PCIRFCR_IP_MSK (0x00800000)
|
||
|
|
#define MCF_PCIRFCR_GR(x) (((x)&0x00000007)<<24)
|
||
|
|
|
||
|
|
/* Bit definitions and macros for MCF_PCIRFAR */
|
||
|
|
#define MCF_PCIRFAR_ALARM(x) (((x)&0x0000007F)<<0)
|
||
|
|
|
||
|
|
/* Bit definitions and macros for MCF_PCIRFRPR */
|
||
|
|
#define MCF_PCIRFRPR_READ(x) (((x)&0x00000FFF)<<0)
|
||
|
|
|
||
|
|
/* Bit definitions and macros for MCF_PCIRFWPR */
|
||
|
|
#define MCF_PCIRFWPR_WRITE(x) (((x)&0x00000FFF)<<0)
|
||
|
|
|
||
|
|
|
||
|
|
/* Bit definitions and macros for MCF_PCIARB_PACR */
|
||
|
|
#define MCF_PCIARB_PACR_INTMPRI (0x00000001)
|
||
|
|
#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1)
|
||
|
|
#define MCF_PCIARB_PACR_INTMINTEN (0x00010000)
|
||
|
|
#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17)
|
||
|
|
#define MCF_PCIARB_PACR_PKMD (0x40000000)
|
||
|
|
#define MCF_PCIARB_PACR_DS (0x80000000)
|
||
|
|
|
||
|
|
/* Bit definitions and macros for MCF_PCIARB_PASR */
|
||
|
|
#define MCF_PCIARB_PASR_ITLMBK (0x00010000)
|
||
|
|
#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17)
|
||
|
|
|
||
|
|
#endif /* __MCF548X_PCI_H__ */
|