mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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593 lines
12 KiB
C
593 lines
12 KiB
C
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/*
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* drivers/pwm/atmel-pwm.c
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*
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* Copyright (C) 2010 Bill Gatliff <bgat@billgatliff.com>
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* Copyright (C) 2007 David Brownell
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*
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* This program is free software; you may redistribute and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/pwm/pwm.h>
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enum {
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/* registers common to the PWMC peripheral */
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PWMC_MR = 0,
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PWMC_ENA = 4,
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PWMC_DIS = 8,
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PWMC_SR = 0xc,
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PWMC_IER = 0x10,
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PWMC_IDR = 0x14,
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PWMC_IMR = 0x18,
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PWMC_ISR = 0x1c,
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/* registers per each PWMC channel */
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PWMC_CMR = 0,
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PWMC_CDTY = 4,
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PWMC_CPRD = 8,
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PWMC_CCNT = 0xc,
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PWMC_CUPD = 0x10,
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/* how to find each channel */
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PWMC_CHAN_BASE = 0x200,
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PWMC_CHAN_STRIDE = 0x20,
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/* CMR bits of interest */
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PWMC_CMR_CPD = 10,
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PWMC_CMR_CPOL = 9,
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PWMC_CMR_CALG = 8,
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PWMC_CMR_CPRE_MASK = 0xf,
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};
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struct atmel_pwm {
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struct pwm_device pwm;
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spinlock_t lock;
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void __iomem *iobase;
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struct clk *clk;
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u32 *sync_mask;
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int irq;
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u32 ccnt_mask;
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};
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static inline struct atmel_pwm *to_atmel_pwm(const struct pwm_channel *p)
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{
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return container_of(p->pwm, struct atmel_pwm, pwm);
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}
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static inline void
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pwmc_writel(const struct atmel_pwm *p,
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unsigned offset, u32 val)
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{
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__raw_writel(val, p->iobase + offset);
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}
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static inline u32
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pwmc_readl(const struct atmel_pwm *p,
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unsigned offset)
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{
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return __raw_readl(p->iobase + offset);
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}
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static inline void
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pwmc_chan_writel(const struct pwm_channel *p,
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u32 offset, u32 val)
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{
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const struct atmel_pwm *ap = to_atmel_pwm(p);
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if (PWMC_CMR == offset)
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val &= ((1 << PWMC_CMR_CPD)
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| (1 << PWMC_CMR_CPOL)
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| (1 << PWMC_CMR_CALG)
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| (PWMC_CMR_CPRE_MASK));
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else
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val &= ap->ccnt_mask;
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pwmc_writel(ap, offset + PWMC_CHAN_BASE
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+ (p->chan * PWMC_CHAN_STRIDE), val);
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}
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static inline u32
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pwmc_chan_readl(const struct pwm_channel *p,
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u32 offset)
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{
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const struct atmel_pwm *ap = to_atmel_pwm(p);
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return pwmc_readl(ap, offset + PWMC_CHAN_BASE
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+ (p->chan * PWMC_CHAN_STRIDE));
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}
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static inline int
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__atmel_pwm_is_on(struct pwm_channel *p)
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{
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struct atmel_pwm *ap = to_atmel_pwm(p);
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return (pwmc_readl(ap, PWMC_SR) & (1 << p->chan)) ? 1 : 0;
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}
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static inline void
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__atmel_pwm_unsynchronize(struct pwm_channel *p,
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struct pwm_channel *to_p)
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{
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const struct atmel_pwm *ap = to_atmel_pwm(p);
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int wchan;
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if (to_p) {
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ap->sync_mask[p->chan] &= ~(1 << to_p->chan);
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ap->sync_mask[to_p->chan] &= ~(1 << p->chan);
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goto done;
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}
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ap->sync_mask[p->chan] = 0;
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for (wchan = 0; wchan < ap->pwm.nchan; wchan++)
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ap->sync_mask[wchan] &= ~(1 << p->chan);
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done:
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dev_dbg(p->pwm->dev, "sync_mask %x\n", ap->sync_mask[p->chan]);
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}
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static inline void
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__atmel_pwm_synchronize(struct pwm_channel *p,
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struct pwm_channel *to_p)
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{
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const struct atmel_pwm *ap = to_atmel_pwm(p);
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if (!to_p)
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return;
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ap->sync_mask[p->chan] |= (1 << to_p->chan);
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ap->sync_mask[to_p->chan] |= (1 << p->chan);
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dev_dbg(p->pwm->dev, "sync_mask %x\n", ap->sync_mask[p->chan]);
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}
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static inline void
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__atmel_pwm_stop(struct pwm_channel *p)
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{
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struct atmel_pwm *ap = to_atmel_pwm(p);
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u32 chid = 1 << p->chan;
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pwmc_writel(ap, PWMC_DIS, ap->sync_mask[p->chan] | chid);
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}
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static inline void
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__atmel_pwm_start(struct pwm_channel *p)
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{
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struct atmel_pwm *ap = to_atmel_pwm(p);
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u32 chid = 1 << p->chan;
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pwmc_writel(ap, PWMC_ENA, ap->sync_mask[p->chan] | chid);
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}
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static int
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atmel_pwm_synchronize(struct pwm_channel *p,
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struct pwm_channel *to_p)
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{
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unsigned long flags;
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spin_lock_irqsave(&p->lock, flags);
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__atmel_pwm_synchronize(p, to_p);
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spin_unlock_irqrestore(&p->lock, flags);
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return 0;
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}
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static int
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atmel_pwm_unsynchronize(struct pwm_channel *p,
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struct pwm_channel *from_p)
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{
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unsigned long flags;
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spin_lock_irqsave(&p->lock, flags);
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__atmel_pwm_unsynchronize(p, from_p);
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spin_unlock_irqrestore(&p->lock, flags);
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return 0;
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}
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static inline int
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__atmel_pwm_config_polarity(struct pwm_channel *p,
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struct pwm_channel_config *c)
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{
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u32 cmr = pwmc_chan_readl(p, PWMC_CMR);
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if (c->polarity)
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cmr &= ~BIT(PWMC_CMR_CPOL);
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else
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cmr |= BIT(PWMC_CMR_CPOL);
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pwmc_chan_writel(p, PWMC_CMR, cmr);
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p->active_high = c->polarity ? 1 : 0;
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dev_dbg(p->pwm->dev, "polarity %d\n", c->polarity);
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return 0;
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}
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static inline int
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__atmel_pwm_config_duty_ticks(struct pwm_channel *p,
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struct pwm_channel_config *c)
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{
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u32 cmr, cprd, cpre, cdty;
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cmr = pwmc_chan_readl(p, PWMC_CMR);
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cprd = pwmc_chan_readl(p, PWMC_CPRD);
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cpre = cmr & PWMC_CMR_CPRE_MASK;
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cmr &= ~BIT(PWMC_CMR_CPD);
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cdty = cprd - (c->duty_ticks >> cpre);
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p->duty_ticks = c->duty_ticks;
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if (__atmel_pwm_is_on(p)) {
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pwmc_chan_writel(p, PWMC_CMR, cmr);
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pwmc_chan_writel(p, PWMC_CUPD, cdty);
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} else
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pwmc_chan_writel(p, PWMC_CDTY, cdty);
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dev_dbg(p->pwm->dev, "duty_ticks = %lu cprd = %x"
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" cdty = %x cpre = %x\n", p->duty_ticks,
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cprd, cdty, cpre);
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return 0;
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}
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static inline int
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__atmel_pwm_config_period_ticks(struct pwm_channel *p,
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struct pwm_channel_config *c)
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{
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u32 cmr, cprd, cpre;
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cpre = fls(c->period_ticks);
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if (cpre < 16)
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cpre = 0;
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else {
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cpre -= 15;
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if (cpre > 10)
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return -EINVAL;
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}
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cmr = pwmc_chan_readl(p, PWMC_CMR);
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cmr &= ~PWMC_CMR_CPRE_MASK;
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cmr |= cpre;
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cprd = c->period_ticks >> cpre;
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pwmc_chan_writel(p, PWMC_CMR, cmr);
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pwmc_chan_writel(p, PWMC_CPRD, cprd);
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p->period_ticks = c->period_ticks;
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dev_dbg(p->pwm->dev, "period_ticks = %lu cprd = %x cpre = %x\n",
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p->period_ticks, cprd, cpre);
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return 0;
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}
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static int
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atmel_pwm_config_nosleep(struct pwm_channel *p,
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struct pwm_channel_config *c)
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{
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int ret = 0;
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unsigned long flags;
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spin_lock_irqsave(&p->lock, flags);
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switch (c->config_mask) {
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case PWM_CONFIG_DUTY_TICKS:
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__atmel_pwm_config_duty_ticks(p, c);
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break;
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case PWM_CONFIG_STOP:
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__atmel_pwm_stop(p);
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break;
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case PWM_CONFIG_START:
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__atmel_pwm_start(p);
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break;
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case PWM_CONFIG_POLARITY:
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__atmel_pwm_config_polarity(p, c);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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spin_unlock_irqrestore(&p->lock, flags);
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return ret;
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}
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static int
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atmel_pwm_stop_sync(struct pwm_channel *p)
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{
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struct atmel_pwm *ap = container_of(p->pwm, struct atmel_pwm, pwm);
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int ret;
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int was_on = __atmel_pwm_is_on(p);
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if (was_on) {
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do {
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init_completion(&p->complete);
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set_bit(FLAG_STOP, &p->flags);
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pwmc_writel(ap, PWMC_IER, 1 << p->chan);
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dev_dbg(p->pwm->dev, "waiting on stop_sync completion...\n");
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ret = wait_for_completion_interruptible(&p->complete);
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dev_dbg(p->pwm->dev, "stop_sync complete (%d)\n", ret);
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if (ret)
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return ret;
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} while (p->flags & BIT(FLAG_STOP));
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}
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return was_on;
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}
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static int
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atmel_pwm_config(struct pwm_channel *p,
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struct pwm_channel_config *c)
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{
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int was_on = 0;
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if (p->pwm->config_nosleep) {
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if (!p->pwm->config_nosleep(p, c))
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return 0;
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}
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might_sleep();
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dev_dbg(p->pwm->dev, "config_mask %x\n", c->config_mask);
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was_on = atmel_pwm_stop_sync(p);
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if (was_on < 0)
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return was_on;
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if (c->config_mask & PWM_CONFIG_PERIOD_TICKS) {
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__atmel_pwm_config_period_ticks(p, c);
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if (!(c->config_mask & PWM_CONFIG_DUTY_TICKS)) {
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struct pwm_channel_config d = {
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.config_mask = PWM_CONFIG_DUTY_TICKS,
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.duty_ticks = p->duty_ticks,
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};
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__atmel_pwm_config_duty_ticks(p, &d);
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}
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}
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if (c->config_mask & PWM_CONFIG_DUTY_TICKS)
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__atmel_pwm_config_duty_ticks(p, c);
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if (c->config_mask & PWM_CONFIG_POLARITY)
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__atmel_pwm_config_polarity(p, c);
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if ((c->config_mask & PWM_CONFIG_START)
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|| (was_on && !(c->config_mask & PWM_CONFIG_STOP)))
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__atmel_pwm_start(p);
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return 0;
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}
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static void
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__atmel_pwm_set_callback(struct pwm_channel *p,
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pwm_callback_t callback)
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{
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struct atmel_pwm *ap = container_of(p->pwm, struct atmel_pwm, pwm);
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p->callback = callback;
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pwmc_writel(ap, p->callback ? PWMC_IER : PWMC_IDR, 1 << p->chan);
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}
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static int
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atmel_pwm_set_callback(struct pwm_channel *p,
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pwm_callback_t callback)
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{
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struct atmel_pwm *ap = to_atmel_pwm(p);
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unsigned long flags;
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spin_lock_irqsave(&ap->lock, flags);
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__atmel_pwm_set_callback(p, callback);
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spin_unlock_irqrestore(&ap->lock, flags);
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return 0;
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}
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static int
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atmel_pwm_request(struct pwm_channel *p)
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{
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struct atmel_pwm *ap = to_atmel_pwm(p);
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unsigned long flags;
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spin_lock_irqsave(&p->lock, flags);
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clk_enable(ap->clk);
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p->tick_hz = clk_get_rate(ap->clk);
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__atmel_pwm_unsynchronize(p, NULL);
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__atmel_pwm_stop(p);
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spin_unlock_irqrestore(&p->lock, flags);
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return 0;
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}
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static void
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atmel_pwm_free(struct pwm_channel *p)
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{
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struct atmel_pwm *ap = to_atmel_pwm(p);
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clk_disable(ap->clk);
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}
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static irqreturn_t
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atmel_pwmc_irq(int irq, void *data)
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{
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struct atmel_pwm *ap = data;
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struct pwm_channel *p;
|
||
|
u32 isr;
|
||
|
int chid;
|
||
|
unsigned long flags;
|
||
|
|
||
|
spin_lock_irqsave(&ap->lock, flags);
|
||
|
|
||
|
isr = pwmc_readl(ap, PWMC_ISR);
|
||
|
for (chid = 0; isr; chid++, isr >>= 1) {
|
||
|
p = &ap->pwm.channels[chid];
|
||
|
if (isr & 1) {
|
||
|
if (p->callback)
|
||
|
p->callback(p);
|
||
|
if (p->flags & BIT(FLAG_STOP)) {
|
||
|
__atmel_pwm_stop(p);
|
||
|
clear_bit(FLAG_STOP, &p->flags);
|
||
|
}
|
||
|
complete_all(&p->complete);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
spin_unlock_irqrestore(&ap->lock, flags);
|
||
|
|
||
|
return IRQ_HANDLED;
|
||
|
}
|
||
|
|
||
|
static int __devinit
|
||
|
atmel_pwmc_probe(struct platform_device *pdev)
|
||
|
{
|
||
|
struct atmel_pwm *ap;
|
||
|
struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||
|
int ret = 0;
|
||
|
|
||
|
ap = kzalloc(sizeof(*ap), GFP_KERNEL);
|
||
|
if (!ap) {
|
||
|
ret = -ENOMEM;
|
||
|
goto err_atmel_pwm_alloc;
|
||
|
}
|
||
|
|
||
|
spin_lock_init(&ap->lock);
|
||
|
platform_set_drvdata(pdev, ap);
|
||
|
|
||
|
ap->pwm.dev = &pdev->dev;
|
||
|
ap->pwm.bus_id = dev_name(&pdev->dev);
|
||
|
|
||
|
ap->pwm.nchan = 4; /* TODO: true only for SAM9263 and AP7000 */
|
||
|
ap->ccnt_mask = 0xffffUL; /* TODO: true only for SAM9263 */
|
||
|
|
||
|
ap->sync_mask = kzalloc(ap->pwm.nchan * sizeof(u32), GFP_KERNEL);
|
||
|
if (!ap->sync_mask) {
|
||
|
ret = -ENOMEM;
|
||
|
goto err_alloc_sync_masks;
|
||
|
}
|
||
|
|
||
|
ap->pwm.owner = THIS_MODULE;
|
||
|
ap->pwm.request = atmel_pwm_request;
|
||
|
ap->pwm.free = atmel_pwm_free;
|
||
|
ap->pwm.config_nosleep = atmel_pwm_config_nosleep;
|
||
|
ap->pwm.config = atmel_pwm_config;
|
||
|
ap->pwm.synchronize = atmel_pwm_synchronize;
|
||
|
ap->pwm.unsynchronize = atmel_pwm_unsynchronize;
|
||
|
ap->pwm.set_callback = atmel_pwm_set_callback;
|
||
|
|
||
|
ap->clk = clk_get(&pdev->dev, "pwm_clk");
|
||
|
if (PTR_ERR(ap->clk)) {
|
||
|
ret = -ENODEV;
|
||
|
goto err_clk_get;
|
||
|
}
|
||
|
|
||
|
ap->iobase = ioremap_nocache(r->start, r->end - r->start + 1);
|
||
|
if (!ap->iobase) {
|
||
|
ret = -ENODEV;
|
||
|
goto err_ioremap;
|
||
|
}
|
||
|
|
||
|
clk_enable(ap->clk);
|
||
|
pwmc_writel(ap, PWMC_DIS, -1);
|
||
|
pwmc_writel(ap, PWMC_IDR, -1);
|
||
|
clk_disable(ap->clk);
|
||
|
|
||
|
ap->irq = platform_get_irq(pdev, 0);
|
||
|
if (ap->irq != -ENXIO) {
|
||
|
ret = request_irq(ap->irq, atmel_pwmc_irq, 0,
|
||
|
ap->pwm.bus_id, ap);
|
||
|
if (ret)
|
||
|
goto err_request_irq;
|
||
|
}
|
||
|
|
||
|
ret = pwm_register(&ap->pwm);
|
||
|
if (ret)
|
||
|
goto err_pwm_register;
|
||
|
|
||
|
return 0;
|
||
|
|
||
|
err_pwm_register:
|
||
|
if (ap->irq != -ENXIO)
|
||
|
free_irq(ap->irq, ap);
|
||
|
err_request_irq:
|
||
|
iounmap(ap->iobase);
|
||
|
err_ioremap:
|
||
|
clk_put(ap->clk);
|
||
|
err_clk_get:
|
||
|
platform_set_drvdata(pdev, NULL);
|
||
|
err_alloc_sync_masks:
|
||
|
kfree(ap);
|
||
|
err_atmel_pwm_alloc:
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
static int __devexit
|
||
|
atmel_pwmc_remove(struct platform_device *pdev)
|
||
|
{
|
||
|
struct atmel_pwm *ap = platform_get_drvdata(pdev);
|
||
|
int ret;
|
||
|
|
||
|
/* TODO: what can we do if this fails? */
|
||
|
ret = pwm_unregister(&ap->pwm);
|
||
|
|
||
|
clk_enable(ap->clk);
|
||
|
pwmc_writel(ap, PWMC_IDR, -1);
|
||
|
pwmc_writel(ap, PWMC_DIS, -1);
|
||
|
clk_disable(ap->clk);
|
||
|
|
||
|
if (ap->irq != -ENXIO)
|
||
|
free_irq(ap->irq, ap);
|
||
|
|
||
|
clk_put(ap->clk);
|
||
|
iounmap(ap->iobase);
|
||
|
|
||
|
kfree(ap);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static struct platform_driver atmel_pwm_driver = {
|
||
|
.driver = {
|
||
|
.name = "atmel_pwmc",
|
||
|
.owner = THIS_MODULE,
|
||
|
},
|
||
|
.probe = atmel_pwmc_probe,
|
||
|
.remove = __devexit_p(atmel_pwmc_remove),
|
||
|
};
|
||
|
|
||
|
static int __init atmel_pwm_init(void)
|
||
|
{
|
||
|
return platform_driver_register(&atmel_pwm_driver);
|
||
|
}
|
||
|
module_init(atmel_pwm_init);
|
||
|
|
||
|
static void __exit atmel_pwm_exit(void)
|
||
|
{
|
||
|
platform_driver_unregister(&atmel_pwm_driver);
|
||
|
}
|
||
|
module_exit(atmel_pwm_exit);
|
||
|
|
||
|
MODULE_AUTHOR("Bill Gatliff <bgat@billgatliff.com>");
|
||
|
MODULE_DESCRIPTION("Driver for Atmel PWMC peripheral");
|
||
|
MODULE_LICENSE("GPL");
|
||
|
MODULE_ALIAS("platform:atmel_pwmc");
|