mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-25 08:50:16 +02:00
94 lines
2.5 KiB
Diff
94 lines
2.5 KiB
Diff
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--- a/arch/mips/amazon/setup.c
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+++ b/arch/mips/amazon/setup.c
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@@ -36,6 +36,12 @@
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#include <asm/amazon/irq.h>
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#include <asm/amazon/model.h>
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+static unsigned int r4k_offset;
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+static unsigned int r4k_cur;
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+
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+/* required in arch/mips/kernel/kspd.c */
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+unsigned long cpu_khz;
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+
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extern void prom_printf(const char * fmt, ...);
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static void amazon_reboot_setup(void);
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@@ -91,35 +97,32 @@ unsigned int amazon_get_cpu_ver(void)
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return cpu_ver;
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}
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-void amazon_time_init(void)
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+static inline u32 amazon_get_counter_resolution(void)
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{
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- mips_hpt_frequency = amazon_get_cpu_hz()/2;
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- printk("mips_hpt_frequency:%d\n", mips_hpt_frequency);
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+ u32 res;
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+ __asm__ __volatile__(
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+ ".set push\n"
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+ ".set mips32r2\n"
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+ ".set noreorder\n"
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+ "rdhwr %0, $3\n"
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+ "ehb\n"
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+ ".set pop\n"
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+ : "=&r" (res)
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+ : /* no input */
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+ : "memory");
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+ instruction_hazard();
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+ return res;
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}
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-extern int hr_time_resolution;
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-
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-/* ISR GPTU Timer 6 for high resolution timer */
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-static void amazon_timer6_interrupt(int irq, void *dev_id)
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+void __init plat_time_init(void)
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{
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- timer_interrupt(AMAZON_TIMER6_INT, NULL);
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-}
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-
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-static struct irqaction hrt_irqaction = {
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- .handler = amazon_timer6_interrupt,
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- .flags = IRQF_DISABLED,
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- .name = "hrt",
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-};
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+ mips_hpt_frequency = amazon_get_cpu_hz() / amazon_get_counter_resolution();
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+ r4k_offset = mips_hpt_frequency / HZ;
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+ printk("mips_hpt_frequency:%d\n", mips_hpt_frequency);
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+ printk("r4k_offset: %08x(%d)\n", r4k_offset, r4k_offset);
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-/*
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- * THe CPU counter for System timer, set to HZ
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- * GPTU Timer 6 for high resolution timer, set to hr_time_resolution
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- * Also misuse this routine to print out the CPU type and clock.
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- */
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-void __init plat_timer_setup(struct irqaction *irq)
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-{
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- /* cpu counter for timer interrupts */
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- setup_irq(MIPS_CPU_TIMER_IRQ, irq);
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+ r4k_cur = (read_c0_count() + r4k_offset);
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+ write_c0_compare(r4k_cur);
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/* enable the timer in the PMU */
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amazon_writel(amazon_readl(AMAZON_PMU_PWDCR)| AMAZON_PMU_PWDCR_GPT|AMAZON_PMU_PWDCR_FPI, AMAZON_PMU_PWDCR);
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@@ -147,7 +150,6 @@ void __init plat_mem_setup(void)
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}
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amazon_reboot_setup();
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- board_time_init = amazon_time_init;
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//stop reset TPE and DFE
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amazon_writel(0, AMAZON_RST_REQ);
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--- a/arch/mips/amazon/interrupt.c
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+++ b/arch/mips/amazon/interrupt.c
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@@ -184,3 +184,10 @@ void __init arch_init_irq(void)
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set_irq_chip(i, &amazon_irq_type);
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}
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}
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+
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+void __cpuinit arch_fixup_c0_irqs(void)
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+{
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+ /* FIXME: check for CPUID and only do fix for specific chips/versions */
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+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
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+ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
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+}
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