mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-20 00:58:25 +02:00
62 lines
2.1 KiB
Diff
62 lines
2.1 KiB
Diff
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--- a/arch/arm/mach-cns3xxx/core.c
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+++ b/arch/arm/mach-cns3xxx/core.c
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@@ -15,6 +15,7 @@
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/mach/irq.h>
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+#include <asm/hardware/cache-l2x0.h>
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#include <asm/hardware/gic.h>
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#include <asm/smp_twd.h>
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#include <mach/cns3xxx.h>
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@@ -71,15 +72,29 @@ static struct map_desc cns3xxx_io_desc[]
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.pfn = __phys_to_pfn(CNS3XXX_SSP_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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+ }, {
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+ .virtual = CNS3XXX_L2C_BASE_VIRT,
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+ .pfn = __phys_to_pfn(CNS3XXX_L2C_BASE),
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+ .length = SZ_4K,
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+ .type = MT_DEVICE,
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},
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};
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void __init cns3xxx_map_io(void)
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{
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+ iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
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+#ifdef CONFIG_CACHE_L2X0
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+ void __iomem *l2x0_base = (void __iomem *) CNS3XXX_L2C_BASE_VIRT;
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+
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+ /* set RAM latencies to 1 cycle for this core tile. */
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+ writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
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+ writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
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+
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+ l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
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+#endif
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#ifdef CONFIG_LOCAL_TIMERS
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twd_base = (void __iomem *) CNS3XXX_TC11MP_TWD_BASE_VIRT;
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#endif
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- iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
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}
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/* used by entry-macro.S */
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--- a/arch/arm/mm/Kconfig
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+++ b/arch/arm/mm/Kconfig
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@@ -821,7 +821,7 @@ config CACHE_L2X0
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depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
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REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
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ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
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- ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
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+ ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_CNS3XXX
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default y
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select OUTER_CACHE
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select OUTER_CACHE_SYNC
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@@ -866,7 +866,7 @@ config ARM_L1_CACHE_SHIFT
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config ARM_DMA_MEM_BUFFERABLE
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bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
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depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
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- MACH_REALVIEW_PB11MP)
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+ MACH_REALVIEW_PB11MP || ARCH_CNS3XXX)
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default y if CPU_V6 || CPU_V6K || CPU_V7
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help
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Historically, the kernel has used strongly ordered mappings to
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