mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-10 14:09:42 +02:00
82 lines
1.7 KiB
C
82 lines
1.7 KiB
C
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/*
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* setup.c - boot time setup code
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*/
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/irq.h>
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#include <linux/ioport.h>
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#include <linux/pm.h>
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#include <asm/bootinfo.h>
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#include <asm/mipsregs.h>
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#include <asm/pgtable.h>
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#include <asm/reboot.h>
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#include <asm/addrspace.h> /* for KSEG1ADDR() */
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/rc32434/rc32434.h>
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#include <asm/rc32434/pci.h>
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#ifdef CONFIG_PCI
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extern void rc32434_time_init(void);
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extern int __init rc32434_pcibridge_init(void);
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#endif
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#define epldMask ((volatile unsigned char *)0xB900000d)
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static void rb_machine_restart(char *command)
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{
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/* just jump to the reset vector */
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* (volatile unsigned *) KSEG1ADDR(0x18008000) = 0x80000001;
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((void (*)(void))KSEG1ADDR(0x1FC00000u))();
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}
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static void rb_machine_halt(void)
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{
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for(;;) continue;
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}
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#ifdef CONFIG_CPU_HAS_WB
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void (*__wbflush) (void);
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static void rb_write_buffer_flush(void)
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{
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__asm__ __volatile__
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("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
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}
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#endif
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void __init plat_mem_setup(void)
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{
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unsigned int pciCntlVal;
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//board_time_init = rc32434_time_init;
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#ifdef CONFIG_CPU_HAS_WB
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__wbflush = rb_write_buffer_flush;
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#endif
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_machine_restart = rb_machine_restart;
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_machine_halt = rb_machine_halt;
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/*_machine_power_off = rb_machine_power_halt;*/
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pm_power_off = rb_machine_halt;
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set_io_port_base(KSEG1);
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pciCntlVal=rc32434_pci->pcic;
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pciCntlVal &= 0xFFFFFF7;
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rc32434_pci->pcic = pciCntlVal;
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#ifdef CONFIG_PCI
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/* Enable PCI interrupts in EPLD Mask register */
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*epldMask = 0x0;
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*(epldMask + 1) = 0x0;
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#endif
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write_c0_wired(0);
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}
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const char *get_system_type(void)
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{
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return "MIPS RB500";
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}
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