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git://projects.qi-hardware.com/openwrt-xburst.git
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94 lines
3.2 KiB
Diff
94 lines
3.2 KiB
Diff
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From db1cc4ee366bf0528fcb8b4afa65dec915d98889 Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <florian@openwrt.org>
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Date: Wed, 25 Jan 2012 17:39:55 +0100
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Subject: [PATCH 04/63] MIPS: BCM63XX: be consistent in clock bits enable naming
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Remove the _CLK suffix from the BCM6368 clock bits definitions to be
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consistent with what is already present.
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Signed-off-by: Florian Fainelli <florian@openwrt.org>
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---
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arch/mips/bcm63xx/clk.c | 6 ++--
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 36 ++++++++++----------
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2 files changed, 21 insertions(+), 21 deletions(-)
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--- a/arch/mips/bcm63xx/clk.c
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+++ b/arch/mips/bcm63xx/clk.c
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@@ -120,7 +120,7 @@ static void enetsw_set(struct clk *clk,
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{
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if (!BCMCPU_IS_6368())
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return;
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- bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
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+ bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
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CKCTL_6368_SWPKT_USB_EN |
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CKCTL_6368_SWPKT_SAR_EN, enable);
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if (enable) {
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@@ -163,7 +163,7 @@ static void usbh_set(struct clk *clk, in
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if (BCMCPU_IS_6348())
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bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
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else if (BCMCPU_IS_6368())
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- bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
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+ bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
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}
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static struct clk clk_usbh = {
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@@ -199,7 +199,7 @@ static void xtm_set(struct clk *clk, int
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if (!BCMCPU_IS_6368())
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return;
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- bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
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+ bcm_hwclock_set(CKCTL_6368_SAR_EN |
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CKCTL_6368_SWPKT_SAR_EN, enable);
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if (enable) {
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -90,29 +90,29 @@
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#define CKCTL_6368_PHYMIPS_EN (1 << 6)
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#define CKCTL_6368_SWPKT_USB_EN (1 << 7)
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#define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
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-#define CKCTL_6368_SPI_CLK_EN (1 << 9)
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-#define CKCTL_6368_USBD_CLK_EN (1 << 10)
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-#define CKCTL_6368_SAR_CLK_EN (1 << 11)
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-#define CKCTL_6368_ROBOSW_CLK_EN (1 << 12)
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-#define CKCTL_6368_UTOPIA_CLK_EN (1 << 13)
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-#define CKCTL_6368_PCM_CLK_EN (1 << 14)
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-#define CKCTL_6368_USBH_CLK_EN (1 << 15)
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+#define CKCTL_6368_SPI_EN (1 << 9)
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+#define CKCTL_6368_USBD_EN (1 << 10)
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+#define CKCTL_6368_SAR_EN (1 << 11)
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+#define CKCTL_6368_ROBOSW_EN (1 << 12)
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+#define CKCTL_6368_UTOPIA_EN (1 << 13)
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+#define CKCTL_6368_PCM_EN (1 << 14)
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+#define CKCTL_6368_USBH_EN (1 << 15)
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#define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
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-#define CKCTL_6368_NAND_CLK_EN (1 << 17)
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-#define CKCTL_6368_IPSEC_CLK_EN (1 << 17)
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+#define CKCTL_6368_NAND_EN (1 << 17)
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+#define CKCTL_6368_IPSEC_EN (1 << 17)
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#define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
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CKCTL_6368_SWPKT_SAR_EN | \
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- CKCTL_6368_SPI_CLK_EN | \
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- CKCTL_6368_USBD_CLK_EN | \
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- CKCTL_6368_SAR_CLK_EN | \
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- CKCTL_6368_ROBOSW_CLK_EN | \
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- CKCTL_6368_UTOPIA_CLK_EN | \
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- CKCTL_6368_PCM_CLK_EN | \
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- CKCTL_6368_USBH_CLK_EN | \
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+ CKCTL_6368_SPI_EN | \
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+ CKCTL_6368_USBD_EN | \
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+ CKCTL_6368_SAR_EN | \
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+ CKCTL_6368_ROBOSW_EN | \
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+ CKCTL_6368_UTOPIA_EN | \
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+ CKCTL_6368_PCM_EN | \
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+ CKCTL_6368_USBH_EN | \
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CKCTL_6368_DISABLE_GLESS_EN | \
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- CKCTL_6368_NAND_CLK_EN | \
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- CKCTL_6368_IPSEC_CLK_EN)
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+ CKCTL_6368_NAND_EN | \
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+ CKCTL_6368_IPSEC_EN)
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/* System PLL Control register */
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#define PERF_SYS_PLL_CTL_REG 0x8
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