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git://projects.qi-hardware.com/openwrt-xburst.git
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99 lines
3.1 KiB
Diff
99 lines
3.1 KiB
Diff
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From c01b6005cfa2d762c2de33d5be2e82f91afaa66f Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Fri, 9 Dec 2011 20:53:47 +0100
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Subject: [PATCH 25/35] MIPS: ath79: add GPIO support code for AR934X
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
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---
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arch/mips/ath79/gpio.c | 47 +++++++++++++++++++++++-
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
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2 files changed, 47 insertions(+), 1 deletions(-)
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--- a/arch/mips/ath79/gpio.c
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+++ b/arch/mips/ath79/gpio.c
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@@ -1,9 +1,12 @@
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/*
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* Atheros AR71XX/AR724X/AR913X GPIO API support
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*
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- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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+ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
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+ *
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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@@ -89,6 +92,42 @@ static int ath79_gpio_direction_output(s
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return 0;
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}
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+static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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+{
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+ void __iomem *base = ath79_gpio_base;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&ath79_gpio_lock, flags);
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+
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+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
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+ base + AR71XX_GPIO_REG_OE);
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+
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+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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+
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+ return 0;
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+}
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+
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+static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
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+ int value)
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+{
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+ void __iomem *base = ath79_gpio_base;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&ath79_gpio_lock, flags);
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+
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+ if (value)
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+ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
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+ else
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+ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
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+
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+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
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+ base + AR71XX_GPIO_REG_OE);
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+
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+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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+
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+ return 0;
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+}
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+
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static struct gpio_chip ath79_gpio_chip = {
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.label = "ath79",
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.get = ath79_gpio_get_value,
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@@ -155,11 +194,17 @@ void __init ath79_gpio_init(void)
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ath79_gpio_count = AR913X_GPIO_COUNT;
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else if (soc_is_ar933x())
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ath79_gpio_count = AR933X_GPIO_COUNT;
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+ else if (soc_is_ar934x())
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+ ath79_gpio_count = AR934X_GPIO_COUNT;
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else
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BUG();
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ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
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ath79_gpio_chip.ngpio = ath79_gpio_count;
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+ if (soc_is_ar934x()) {
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+ ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
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+ ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
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+ }
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err = gpiochip_add(&ath79_gpio_chip);
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if (err)
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -367,5 +367,6 @@
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#define AR724X_GPIO_COUNT 18
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#define AR913X_GPIO_COUNT 22
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#define AR933X_GPIO_COUNT 30
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+#define AR934X_GPIO_COUNT 23
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#endif /* __ASM_MACH_AR71XX_REGS_H */
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