mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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266 lines
7.3 KiB
C
266 lines
7.3 KiB
C
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/*
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* linux/include/asm-mips/mach-jz4740/dma.h
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*
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* JZ4740 DMA definition.
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*
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* Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
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*
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* Author: <lhhuang@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_JZ4740_DMA_H__
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#define __ASM_JZ4740_DMA_H__
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#include <linux/interrupt.h>
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#include <asm/io.h> /* need byte IO */
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#include <linux/spinlock.h> /* And spinlocks */
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#include <linux/delay.h>
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#include <asm/system.h>
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/*
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* Descriptor structure for JZ4740 DMA engine
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* Note: this structure must always be aligned to a 16-bytes boundary.
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*/
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typedef struct {
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volatile u32 dcmd; /* DCMD value for the current transfer */
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volatile u32 dsadr; /* DSAR value for the current transfer */
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volatile u32 dtadr; /* DTAR value for the current transfer */
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volatile u32 ddadr; /* Points to the next descriptor + transfer count */
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} jz_dma_desc;
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/* DMA Device ID's follow */
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enum {
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DMA_ID_UART0_TX = 0,
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DMA_ID_UART0_RX,
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DMA_ID_SSI_TX,
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DMA_ID_SSI_RX,
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DMA_ID_AIC_TX,
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DMA_ID_AIC_RX,
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DMA_ID_MSC_TX,
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DMA_ID_MSC_RX,
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DMA_ID_TCU_OVERFLOW,
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DMA_ID_AUTO,
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DMA_ID_RAW_SET,
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DMA_ID_MAX
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};
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/* DMA modes, simulated by sw */
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#define DMA_MODE_READ 0x0 /* I/O to memory, no autoinit, increment, single mode */
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#define DMA_MODE_WRITE 0x1 /* memory to I/O, no autoinit, increment, single mode */
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#define DMA_AUTOINIT 0x2
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#define DMA_MODE_MASK 0x3
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struct jz_dma_chan {
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int dev_id; /* DMA ID: this channel is allocated if >=0, free otherwise */
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unsigned int io; /* DMA channel number */
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const char *dev_str; /* string describes the DMA channel */
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int irq; /* DMA irq number */
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void *irq_dev; /* DMA private device structure */
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unsigned int fifo_addr; /* physical fifo address of the requested device */
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unsigned int cntl; /* DMA controll */
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unsigned int mode; /* DMA configuration */
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unsigned int source; /* DMA request source */
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};
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extern struct jz_dma_chan jz_dma_table[];
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#define DMA_8BIT_RX_CMD \
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DMAC_DCMD_DAI | \
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DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 | \
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DMAC_DCMD_DS_8BIT | DMAC_DCMD_RDIL_IGN
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#define DMA_8BIT_TX_CMD \
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DMAC_DCMD_SAI | \
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DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 | \
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DMAC_DCMD_DS_8BIT | DMAC_DCMD_RDIL_IGN
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#define DMA_16BIT_RX_CMD \
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DMAC_DCMD_DAI | \
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DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_32 | \
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DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
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#define DMA_16BIT_TX_CMD \
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DMAC_DCMD_SAI | \
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DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_16 | \
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DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
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#define DMA_32BIT_RX_CMD \
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DMAC_DCMD_DAI | \
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DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \
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DMAC_DCMD_DS_32BIT | DMAC_DCMD_RDIL_IGN
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#define DMA_32BIT_TX_CMD \
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DMAC_DCMD_SAI | \
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DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \
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DMAC_DCMD_DS_32BIT | DMAC_DCMD_RDIL_IGN
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#define DMA_16BYTE_RX_CMD \
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DMAC_DCMD_DAI | \
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DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 | \
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DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
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#define DMA_16BYTE_TX_CMD \
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DMAC_DCMD_SAI | \
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DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 | \
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DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
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#define DMA_32BYTE_RX_CMD \
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DMAC_DCMD_DAI | \
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DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 | \
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DMAC_DCMD_DS_32BYTE | DMAC_DCMD_RDIL_IGN
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#define DMA_32BYTE_TX_CMD \
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DMAC_DCMD_SAI | \
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DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_8 | \
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DMAC_DCMD_DS_32BYTE | DMAC_DCMD_RDIL_IGN
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#define DMA_AIC_32_16BYTE_TX_CMD \
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DMAC_DCMD_SAI | \
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DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \
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DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
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#define DMA_AIC_32_16BYTE_RX_CMD \
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DMAC_DCMD_DAI | \
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DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \
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DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
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#define DMA_AIC_16BIT_TX_CMD \
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DMAC_DCMD_SAI | \
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DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \
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DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
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#define DMA_AIC_16BIT_RX_CMD \
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DMAC_DCMD_DAI | \
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DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \
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DMAC_DCMD_DS_16BIT | DMAC_DCMD_RDIL_IGN
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#define DMA_AIC_16BYTE_RX_CMD \
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DMAC_DCMD_DAI | \
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DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \
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DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
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#define DMA_AIC_16BYTE_TX_CMD \
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DMAC_DCMD_SAI | \
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DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \
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DMAC_DCMD_DS_16BYTE | DMAC_DCMD_RDIL_IGN
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extern int jz_request_dma(int dev_id,
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const char *dev_str,
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irqreturn_t (*irqhandler)(int, void *),
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unsigned long irqflags,
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void *irq_dev_id);
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extern void jz_free_dma(unsigned int dmanr);
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extern int jz_dma_read_proc(char *buf, char **start, off_t fpos,
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int length, int *eof, void *data);
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extern void dump_jz_dma_channel(unsigned int dmanr);
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extern void enable_dma(unsigned int dmanr);
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extern void disable_dma(unsigned int dmanr);
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extern void set_dma_addr(unsigned int dmanr, unsigned int phyaddr);
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extern void set_dma_count(unsigned int dmanr, unsigned int bytecnt);
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extern void set_dma_mode(unsigned int dmanr, unsigned int mode);
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extern void jz_set_oss_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt);
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extern void jz_set_alsa_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt);
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extern unsigned int get_dma_residue(unsigned int dmanr);
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extern spinlock_t dma_spin_lock;
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static __inline__ unsigned long claim_dma_lock(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&dma_spin_lock, flags);
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return flags;
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}
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static __inline__ void release_dma_lock(unsigned long flags)
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{
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spin_unlock_irqrestore(&dma_spin_lock, flags);
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}
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/* Clear the 'DMA Pointer Flip Flop'.
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* Write 0 for LSB/MSB, 1 for MSB/LSB access.
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*/
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#define clear_dma_ff(channel)
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static __inline__ struct jz_dma_chan *get_dma_chan(unsigned int dmanr)
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{
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if (dmanr > MAX_DMA_NUM
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|| jz_dma_table[dmanr].dev_id < 0)
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return NULL;
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return &jz_dma_table[dmanr];
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}
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static __inline__ int dma_halted(unsigned int dmanr)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return 1;
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return __dmac_channel_transmit_halt_detected(dmanr) ? 1 : 0;
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}
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static __inline__ unsigned int get_dma_mode(unsigned int dmanr)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return 0;
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return chan->mode;
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}
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static __inline__ void clear_dma_done(unsigned int dmanr)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
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}
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static __inline__ void clear_dma_halt(unsigned int dmanr)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT);
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REG_DMAC_DMACR &= ~(DMAC_DMACR_HLT);
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}
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static __inline__ void clear_dma_flag(unsigned int dmanr)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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REG_DMAC_DCCSR(chan->io) &= ~(DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
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REG_DMAC_DMACR &= ~(DMAC_DMACR_HLT | DMAC_DMACR_AR);
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}
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static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
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{
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}
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static __inline__ unsigned int get_dma_done_status(unsigned int dmanr)
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{
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unsigned long dccsr;
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return 0;
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dccsr = REG_DMAC_DCCSR(chan->io);
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return dccsr & (DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
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}
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static __inline__ int get_dma_done_irq(unsigned int dmanr)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return -1;
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return chan->irq;
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}
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#endif /* __ASM_JZ4740_DMA_H__ */
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