mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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95 lines
3.8 KiB
C
95 lines
3.8 KiB
C
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/*
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* Misc utility routines for accessing chip-specific features
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* of Broadcom HNBU SiliconBackplane-based chips.
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*
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* Copyright 2004, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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* $Id$
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*/
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#ifndef _sbutils_h_
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#define _sbutils_h_
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/* Board styles (bustype) */
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#define BOARDSTYLE_SOC 0 /* Silicon Backplane */
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#define BOARDSTYLE_PCI 1 /* PCI/MiniPCI board */
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#define BOARDSTYLE_PCMCIA 2 /* PCMCIA board */
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#define BOARDSTYLE_CARDBUS 3 /* Cardbus board */
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/*
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* Many of the routines below take an 'sbh' handle as their first arg.
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* Allocate this by calling sb_attach(). Free it by calling sb_detach().
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* At any one time, the sbh is logically focused on one particular sb core
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* (the "current core").
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* Use sb_setcore() or sb_setcoreidx() to change the association to another core.
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*/
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/* exported externs */
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extern void *sb_attach(uint pcidev, void *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
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extern void *sb_kattach(void);
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extern void sb_detach(void *sbh);
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extern uint sb_chip(void *sbh);
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extern uint sb_chiprev(void *sbh);
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extern uint sb_chipcrev(void *sbh);
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extern uint sb_chippkg(void *sbh);
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extern uint sb_pcirev(void *sbh);
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extern uint sb_pcmciarev(void *sbh);
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extern uint sb_boardvendor(void *sbh);
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extern uint sb_boardtype(void *sbh);
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extern uint sb_boardstyle(void *sbh);
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extern uint sb_bus(void *sbh);
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extern uint sb_corelist(void *sbh, uint coreid[]);
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extern uint sb_coreid(void *sbh);
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extern uint sb_coreidx(void *sbh);
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extern uint sb_coreunit(void *sbh);
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extern uint sb_corevendor(void *sbh);
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extern uint sb_corerev(void *sbh);
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extern void *sb_coreregs(void *sbh);
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extern uint32 sb_coreflags(void *sbh, uint32 mask, uint32 val);
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extern uint32 sb_coreflagshi(void *sbh, uint32 mask, uint32 val);
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extern bool sb_iscoreup(void *sbh);
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extern void *sb_setcoreidx(void *sbh, uint coreidx);
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extern void *sb_setcore(void *sbh, uint coreid, uint coreunit);
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extern void sb_commit(void *sbh);
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extern uint32 sb_base(uint32 admatch);
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extern uint32 sb_size(uint32 admatch);
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extern void sb_core_reset(void *sbh, uint32 bits);
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extern void sb_core_tofixup(void *sbh);
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extern void sb_core_disable(void *sbh, uint32 bits);
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extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
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extern uint32 sb_clock(void *sbh);
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extern void sb_pci_setup(void *sbh, uint32 *dmaoffset, uint coremask);
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extern void sb_pcmcia_init(void *sbh);
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extern void sb_watchdog(void *sbh, uint ticks);
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extern void *sb_gpiosetcore(void *sbh);
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extern uint32 sb_gpiocontrol(void *sbh, uint32 mask, uint32 val);
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extern uint32 sb_gpioouten(void *sbh, uint32 mask, uint32 val);
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extern uint32 sb_gpioout(void *sbh, uint32 mask, uint32 val);
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extern uint32 sb_gpioin(void *sbh);
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extern uint32 sb_gpiointpolarity(void *sbh, uint32 mask, uint32 val);
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extern uint32 sb_gpiointmask(void *sbh, uint32 mask, uint32 val);
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extern bool sb_taclear(void *sbh);
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extern void sb_pwrctl_init(void *sbh);
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extern uint16 sb_pwrctl_fast_pwrup_delay(void *sbh);
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extern bool sb_pwrctl_clk(void *sbh, uint mode);
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extern int sb_pwrctl_xtal(void *sbh, uint what, bool on);
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extern int sb_pwrctl_slowclk(void *sbh, bool set, uint *div);
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extern void sb_register_intr_callback(void *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
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/* pwrctl xtal what flags */
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#define XTAL 0x1 /* primary crystal oscillator (2050) */
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#define PLL 0x2 /* main chip pll */
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/* pwrctl clk mode */
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#define CLK_FAST 0 /* force fast (pll) clock */
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#define CLK_SLOW 1 /* force slow clock */
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#define CLK_DYNAMIC 2 /* enable dynamic power control */
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#endif /* _sbutils_h_ */
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