2011-04-10 18:08:28 +03:00
|
|
|
--- a/arch/mips/kernel/traps.c
|
|
|
|
|
+++ b/arch/mips/kernel/traps.c
|
2012-05-13 18:10:40 +03:00
|
|
|
@@ -1593,7 +1593,16 @@ void __cpuinit per_cpu_trap_init(void)
|
2011-04-10 18:08:28 +03:00
|
|
|
if (cpu_has_mips_r2) {
|
|
|
|
|
cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
|
|
|
|
|
cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
|
|
|
|
|
+ if (!cp0_compare_irq)
|
|
|
|
|
+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
|
|
|
|
|
+
|
|
|
|
|
cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
|
|
|
|
|
+ if (!cp0_perfcount_irq)
|
|
|
|
|
+ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
|
|
|
|
|
+
|
|
|
|
|
+ if (arch_fixup_c0_irqs)
|
|
|
|
|
+ arch_fixup_c0_irqs();
|
|
|
|
|
+
|
|
|
|
|
if (cp0_perfcount_irq == cp0_compare_irq)
|
|
|
|
|
cp0_perfcount_irq = -1;
|
|
|
|
|
} else {
|
|
|
|
|
--- a/arch/mips/include/asm/irq.h
|
|
|
|
|
+++ b/arch/mips/include/asm/irq.h
|
2012-05-13 18:10:40 +03:00
|
|
|
@@ -139,9 +139,11 @@ extern void free_irqno(unsigned int irq)
|
2011-04-10 18:08:28 +03:00
|
|
|
* IE7. Since R2 their number has to be read from the c0_intctl register.
|
|
|
|
|
*/
|
|
|
|
|
#define CP0_LEGACY_COMPARE_IRQ 7
|
|
|
|
|
+#define CP0_LEGACY_PERFCNT_IRQ 7
|
|
|
|
|
|
|
|
|
|
extern int cp0_compare_irq;
|
|
|
|
|
extern int cp0_compare_irq_shift;
|
|
|
|
|
extern int cp0_perfcount_irq;
|
|
|
|
|
+extern void __weak arch_fixup_c0_irqs(void);
|
|
|
|
|
|
|
|
|
|
#endif /* _ASM_IRQ_H */
|
