mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 15:39:18 +03:00
356 lines
11 KiB
Diff
356 lines
11 KiB
Diff
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From b80a5236053be899421417871d1be8016912e94b Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 3 Aug 2012 09:52:10 +0200
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Subject: [PATCH 05/25] pci support
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---
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arch/mips/include/asm/mach-lantiq/lantiq.h | 37 ++++-----
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.../mips/include/asm/mach-lantiq/lantiq_platform.h | 9 ++
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arch/mips/pci/Makefile | 5 +-
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arch/mips/pci/ops-lantiq.c | 6 +-
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arch/mips/pci/pci-lantiq.c | 82 ++++++++------------
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arch/mips/pci/pci-lantiq.h | 2 +-
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arch/mips/pci/pci.c | 25 ++++++
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7 files changed, 89 insertions(+), 77 deletions(-)
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diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
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index ce2f029..622847f 100644
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--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
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+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
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@@ -9,6 +9,8 @@
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#define _LANTIQ_H__
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#include <linux/irq.h>
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+#include <linux/clk.h>
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+#include <linux/ioport.h>
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/* generic reg access functions */
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#define ltq_r32(reg) __raw_readl(reg)
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@@ -18,40 +20,33 @@
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#define ltq_r8(reg) __raw_readb(reg)
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#define ltq_w8(val, reg) __raw_writeb(val, reg)
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-/* register access macros for EBU and CGU */
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-#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
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-#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
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-#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
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-#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
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-
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-extern __iomem void *ltq_ebu_membase;
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-extern __iomem void *ltq_cgu_membase;
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-
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extern unsigned int ltq_get_cpu_ver(void);
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extern unsigned int ltq_get_soc_type(void);
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-/* clock speeds */
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-#define CLOCK_60M 60000000
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-#define CLOCK_83M 83333333
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-#define CLOCK_111M 111111111
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-#define CLOCK_133M 133333333
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-#define CLOCK_167M 166666667
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-#define CLOCK_200M 200000000
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-#define CLOCK_266M 266666666
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-#define CLOCK_333M 333333333
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-#define CLOCK_400M 400000000
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-
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/* spinlock all ebu i/o */
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extern spinlock_t ebu_lock;
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+/* request a non-gpio and set the PIO config */
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+extern int ltq_gpio_request(struct device *dev, unsigned int pin,
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+ unsigned int mux, unsigned int dir, const char *name);
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+
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/* some irq helpers */
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extern void ltq_disable_irq(struct irq_data *data);
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extern void ltq_mask_and_ack_irq(struct irq_data *data);
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extern void ltq_enable_irq(struct irq_data *data);
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+/* clock handling */
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+extern int clk_activate(struct clk *clk);
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+extern void clk_deactivate(struct clk *clk);
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+extern struct clk *clk_get_cpu(void);
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+extern struct clk *clk_get_fpi(void);
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+extern struct clk *clk_get_io(void);
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+
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/* find out what caused the last cpu reset */
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extern int ltq_reset_cause(void);
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-#define LTQ_RST_CAUSE_WDTRST 0x20
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+
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+/* helper for requesting and remapping resources */
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+extern void __iomem *ltq_remap_resource(struct resource *res);
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#define IOPORT_RESOURCE_START 0x10000000
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#define IOPORT_RESOURCE_END 0xffffffff
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diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
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index a305f1d..38ed938 100644
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--- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
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+++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
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@@ -50,4 +50,13 @@ struct ltq_eth_data {
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int mii_mode;
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};
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+
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+struct ltq_spi_platform_data {
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+ u16 num_chipselect;
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+};
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+
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+struct ltq_spi_controller_data {
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+ unsigned gpio;
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+};
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+
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#endif
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diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
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index c3ac4b0..31e70c5 100644
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--- a/arch/mips/pci/Makefile
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+++ b/arch/mips/pci/Makefile
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@@ -41,7 +41,10 @@ obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
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obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o
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obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o
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obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
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-obj-$(CONFIG_SOC_XWAY) += pci-lantiq.o ops-lantiq.o
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+obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
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+obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
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+obj-$(CONFIG_PCIE_LANTIQ) += pcie-lantiq-phy.o pcie-lantiq.o fixup-lantiq-pcie.o
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+obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o
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obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
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obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
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obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
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diff --git a/arch/mips/pci/ops-lantiq.c b/arch/mips/pci/ops-lantiq.c
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index 1f2afb5..5cbb0cf 100644
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--- a/arch/mips/pci/ops-lantiq.c
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+++ b/arch/mips/pci/ops-lantiq.c
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@@ -41,7 +41,7 @@ static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
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spin_lock_irqsave(&ebu_lock, flags);
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- cfg_base = (unsigned long) ltq_pci_mapped_cfg;
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+ cfg_base = (unsigned long) ltq_pci_cfgbase;
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cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
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LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
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@@ -55,11 +55,11 @@ static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
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wmb();
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/* clean possible Master abort */
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- cfg_base = (unsigned long) ltq_pci_mapped_cfg;
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+ cfg_base = (unsigned long) ltq_pci_cfgbase;
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cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
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temp = ltq_r32(((u32 *)(cfg_base)));
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temp = swab32(temp);
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- cfg_base = (unsigned long) ltq_pci_mapped_cfg;
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+ cfg_base = (unsigned long) ltq_pci_cfgbase;
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cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
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ltq_w32(temp, ((u32 *)cfg_base));
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diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
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index be1e1af..7a29738 100644
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--- a/arch/mips/pci/pci-lantiq.c
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+++ b/arch/mips/pci/pci-lantiq.c
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@@ -65,45 +65,42 @@
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#define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y))
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#define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x))
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-#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y))
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-#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x))
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+#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_cfgbase + (y))
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+#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_cfgbase + (x))
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struct ltq_pci_gpio_map {
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int pin;
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- int alt0;
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- int alt1;
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+ int mux;
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int dir;
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char *name;
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};
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/* the pci core can make use of the following gpios */
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static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = {
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- { 0, 1, 0, 0, "pci-exin0" },
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- { 1, 1, 0, 0, "pci-exin1" },
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- { 2, 1, 0, 0, "pci-exin2" },
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- { 39, 1, 0, 0, "pci-exin3" },
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- { 10, 1, 0, 0, "pci-exin4" },
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- { 9, 1, 0, 0, "pci-exin5" },
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- { 30, 1, 0, 1, "pci-gnt1" },
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- { 23, 1, 0, 1, "pci-gnt2" },
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- { 19, 1, 0, 1, "pci-gnt3" },
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- { 38, 1, 0, 1, "pci-gnt4" },
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- { 29, 1, 0, 0, "pci-req1" },
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- { 31, 1, 0, 0, "pci-req2" },
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- { 3, 1, 0, 0, "pci-req3" },
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- { 37, 1, 0, 0, "pci-req4" },
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+ { 0, 2, 0, "pci-exin0" },
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+ { 1, 2, 0, "pci-exin1" },
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+ { 2, 2, 0, "pci-exin2" },
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+ { 39, 2, 0, "pci-exin3" },
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+ { 10, 2, 0, "pci-exin4" },
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+ { 9, 2, 0, "pci-exin5" },
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+ { 30, 2, 1, "pci-gnt1" },
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+ { 23, 2, 1, "pci-gnt2" },
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+ { 19, 2, 1, "pci-gnt3" },
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+ { 38, 2, 1, "pci-gnt4" },
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+ { 29, 2, 0, "pci-req1" },
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+ { 31, 2, 0, "pci-req2" },
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+ { 3, 2, 0, "pci-req3" },
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+ { 37, 2, 0, "pci-req4" },
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};
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-__iomem void *ltq_pci_mapped_cfg;
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+__iomem void *ltq_pci_cfgbase;
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static __iomem void *ltq_pci_membase;
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-int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
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-
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/* Since the PCI REQ pins can be reused for other functionality, make it
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possible to exclude those from interpretation by the PCI controller */
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static int ltq_pci_req_mask = 0xf;
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-static int *ltq_pci_irq_map;
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+extern int *ltq_pci_irq_map;
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struct pci_ops ltq_pci_ops = {
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.read = ltq_pci_read_config_dword,
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@@ -132,14 +129,6 @@ static struct pci_controller ltq_pci_controller = {
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.io_offset = 0x00000000UL,
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};
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-int pcibios_plat_dev_init(struct pci_dev *dev)
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-{
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- if (ltqpci_plat_dev_init)
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- return ltqpci_plat_dev_init(dev);
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-
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- return 0;
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-}
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-
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static u32 ltq_calc_bar11mask(void)
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{
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u32 mem, bar11mask;
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@@ -151,25 +140,26 @@ static u32 ltq_calc_bar11mask(void)
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return bar11mask;
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}
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-static void ltq_pci_setup_gpio(int gpio)
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+static void ltq_pci_setup_gpio(struct device *dev)
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{
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+ struct ltq_pci_data *conf = (struct ltq_pci_data *) dev->platform_data;
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int i;
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for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) {
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- if (gpio & (1 << i)) {
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- ltq_gpio_request(ltq_pci_gpio_map[i].pin,
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- ltq_pci_gpio_map[i].alt0,
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- ltq_pci_gpio_map[i].alt1,
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+ if (conf->gpio & (1 << i)) {
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+ ltq_gpio_request(dev, ltq_pci_gpio_map[i].pin,
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+ ltq_pci_gpio_map[i].mux,
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ltq_pci_gpio_map[i].dir,
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ltq_pci_gpio_map[i].name);
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}
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}
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- ltq_gpio_request(21, 0, 0, 1, "pci-reset");
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- ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
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+ ltq_gpio_request(dev, 21, 0, 1, "pci-reset");
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+ ltq_pci_req_mask = (conf->gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
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}
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-static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
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+static int __devinit ltq_pci_startup(struct device *dev)
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{
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u32 temp_buffer;
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+ struct ltq_pci_data *conf = (struct ltq_pci_data *) dev->platform_data;
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/* set clock to 33Mhz */
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if (ltq_is_ar9()) {
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@@ -192,7 +182,7 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
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}
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/* setup pci clock and gpis used by pci */
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- ltq_pci_setup_gpio(conf->gpio);
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+ ltq_pci_setup_gpio(dev);
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/* enable auto-switching between PCI and EBU */
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ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
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@@ -256,16 +246,6 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
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return 0;
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}
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-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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-{
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- if (ltq_pci_irq_map[slot])
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- return ltq_pci_irq_map[slot];
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- printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n",
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- slot);
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-
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- return 0;
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-}
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-
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static int __devinit ltq_pci_probe(struct platform_device *pdev)
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{
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struct ltq_pci_data *ltq_pci_data =
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@@ -273,11 +253,11 @@ static int __devinit ltq_pci_probe(struct platform_device *pdev)
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pci_probe_only = 0;
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ltq_pci_irq_map = ltq_pci_data->irq;
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ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE);
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- ltq_pci_mapped_cfg =
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+ ltq_pci_cfgbase =
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ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE);
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ltq_pci_controller.io_map_base =
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(unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1);
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- ltq_pci_startup(ltq_pci_data);
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+ ltq_pci_startup(&pdev->dev);
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register_pci_controller(<q_pci_controller);
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return 0;
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diff --git a/arch/mips/pci/pci-lantiq.h b/arch/mips/pci/pci-lantiq.h
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index 66bf6cd..c4721b4 100644
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--- a/arch/mips/pci/pci-lantiq.h
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+++ b/arch/mips/pci/pci-lantiq.h
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@@ -9,7 +9,7 @@
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#ifndef _LTQ_PCI_H__
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#define _LTQ_PCI_H__
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-extern __iomem void *ltq_pci_mapped_cfg;
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+extern __iomem void *ltq_pci_cfgbase;
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extern int ltq_pci_read_config_dword(struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 *val);
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extern int ltq_pci_write_config_dword(struct pci_bus *bus,
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diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
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index 1552150..cd034a9 100644
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--- a/arch/mips/pci/pci.c
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+++ b/arch/mips/pci/pci.c
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@@ -201,6 +201,31 @@ static int __init pcibios_init(void)
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subsys_initcall(pcibios_init);
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+int pcibios_host_nr(void)
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+{
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+ int count;
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+ struct pci_controller *hose;
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+ for (count = 0, hose = hose_head; hose; hose = hose->next, count++) {
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+ ;
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+ }
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+ return count;
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+}
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+EXPORT_SYMBOL(pcibios_host_nr);
|
||
|
+
|
||
|
+int pcibios_1st_host_bus_nr(void)
|
||
|
+{
|
||
|
+ int bus_nr = 0;
|
||
|
+ struct pci_controller *hose = hose_head;
|
||
|
+
|
||
|
+ if (hose != NULL) {
|
||
|
+ if (hose->bus != NULL) {
|
||
|
+ bus_nr = hose->bus->subordinate + 1;
|
||
|
+ }
|
||
|
+ }
|
||
|
+ return bus_nr;
|
||
|
+}
|
||
|
+EXPORT_SYMBOL(pcibios_1st_host_bus_nr);
|
||
|
+
|
||
|
static int pcibios_enable_resources(struct pci_dev *dev, int mask)
|
||
|
{
|
||
|
u16 cmd, old_cmd;
|
||
|
--
|
||
|
1.7.9.1
|
||
|
|