2010-02-24 15:39:02 +02:00
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/*
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2011-01-14 20:19:13 +02:00
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* Platform driver for the Realtek RTL8366RB ethernet switch
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2010-02-24 15:39:02 +02:00
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*
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* Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
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2011-01-14 20:19:05 +02:00
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* Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
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2010-02-24 15:39:02 +02:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/skbuff.h>
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#include <linux/rtl8366rb.h>
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#include "rtl8366_smi.h"
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
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2011-01-14 20:19:13 +02:00
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#define RTL8366RB_DRIVER_VER "0.2.3"
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_PHY_NO_MAX 4
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#define RTL8366RB_PHY_PAGE_MAX 7
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#define RTL8366RB_PHY_ADDR_MAX 31
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2010-10-27 14:34:36 +03:00
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#define RTL8366RB_PHY_WAN 4
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2010-02-24 15:39:02 +02:00
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2010-06-26 22:54:11 +03:00
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/* Switch Global Configuration register */
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_SGCR 0x0000
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#define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
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#define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
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#define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
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#define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
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#define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
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#define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
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#define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
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2010-07-01 21:08:58 +03:00
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#define RTL8366RB_SGCR_EN_VLAN BIT(13)
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#define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
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2010-06-26 22:54:11 +03:00
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/* Port Enable Control register */
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_PECR 0x0001
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2010-06-26 22:54:11 +03:00
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/* Switch Security Control registers */
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_SSCR0 0x0002
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#define RTL8366RB_SSCR1 0x0003
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#define RTL8366RB_SSCR2 0x0004
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#define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
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2010-06-26 22:54:11 +03:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_RESET_CTRL_REG 0x0100
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#define RTL8366RB_CHIP_CTRL_RESET_HW 1
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#define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
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#define RTL8366RB_CHIP_VERSION_MASK 0xf
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#define RTL8366RB_CHIP_ID_REG 0x0509
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#define RTL8366RB_CHIP_ID_8366 0x5937
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2010-02-24 15:39:02 +02:00
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/* PHY registers control */
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
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#define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_PHY_CTRL_READ 1
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#define RTL8366RB_PHY_CTRL_WRITE 0
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_PHY_REG_MASK 0x1f
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#define RTL8366RB_PHY_PAGE_OFFSET 5
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#define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
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#define RTL8366RB_PHY_NO_OFFSET 9
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#define RTL8366RB_PHY_NO_MASK (0x1f << 9)
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2010-02-24 15:39:02 +02:00
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2010-07-03 10:29:27 +03:00
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#define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
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2010-02-24 15:39:02 +02:00
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/* LED control registers */
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_LED_BLINKRATE_REG 0x0430
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#define RTL8366RB_LED_BLINKRATE_BIT 0
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#define RTL8366RB_LED_BLINKRATE_MASK 0x0007
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_LED_CTRL_REG 0x0431
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#define RTL8366RB_LED_0_1_CTRL_REG 0x0432
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#define RTL8366RB_LED_2_3_CTRL_REG 0x0433
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_MIB_COUNT 33
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#define RTL8366RB_GLOBAL_MIB_COUNT 1
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#define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
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#define RTL8366RB_MIB_COUNTER_BASE 0x1000
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#define RTL8366RB_MIB_CTRL_REG 0x13F0
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#define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
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#define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
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#define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
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#define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
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#define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
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#define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
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(RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
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#define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
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#define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
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#define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
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#define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
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#define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
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2010-02-24 15:39:02 +02:00
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2010-08-16 22:23:53 +03:00
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#define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
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#define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
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#define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
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#define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
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#define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
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#define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
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#define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_PORT_NUM_CPU 5
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#define RTL8366RB_NUM_PORTS 6
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#define RTL8366RB_NUM_VLANS 16
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#define RTL8366RB_NUM_LEDGROUPS 4
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#define RTL8366RB_NUM_VIDS 4096
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#define RTL8366RB_PRIORITYMAX 7
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#define RTL8366RB_FIDMAX 7
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
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#define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
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#define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
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#define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
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#define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
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RTL8366RB_PORT_2 | \
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RTL8366RB_PORT_3 | \
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RTL8366RB_PORT_4 | \
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RTL8366RB_PORT_5 | \
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RTL8366RB_PORT_CPU)
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
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RTL8366RB_PORT_2 | \
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RTL8366RB_PORT_3 | \
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RTL8366RB_PORT_4 | \
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RTL8366RB_PORT_5)
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
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RTL8366RB_PORT_2 | \
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RTL8366RB_PORT_3 | \
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RTL8366RB_PORT_4)
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2010-02-24 15:39:02 +02:00
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2010-07-01 21:07:55 +03:00
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#define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
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2010-02-24 15:39:02 +02:00
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2010-08-16 22:23:53 +03:00
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#define RTL8366RB_VLAN_VID_MASK 0xfff
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#define RTL8366RB_VLAN_PRIORITY_SHIFT 12
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#define RTL8366RB_VLAN_PRIORITY_MASK 0x7
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#define RTL8366RB_VLAN_UNTAG_SHIFT 8
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#define RTL8366RB_VLAN_UNTAG_MASK 0xff
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#define RTL8366RB_VLAN_MEMBER_MASK 0xff
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#define RTL8366RB_VLAN_FID_MASK 0x7
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2010-02-24 15:39:02 +02:00
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2011-01-14 20:19:05 +02:00
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/* Port ingress bandwidth control */
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#define RTL8366RB_IB_BASE 0x0200
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#define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + pnum)
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#define RTL8366RB_IB_BDTH_MASK 0x3fff
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#define RTL8366RB_IB_PREIFG_OFFSET 14
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#define RTL8366RB_IB_PREIFG_MASK (1 << RTL8366RB_IB_PREIFG_OFFSET)
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/* Port egress bandwidth control */
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#define RTL8366RB_EB_BASE 0x02d1
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#define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + pnum)
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#define RTL8366RB_EB_BDTH_MASK 0x3fff
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#define RTL8366RB_EB_PREIFG_REG 0x02f8
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#define RTL8366RB_EB_PREIFG_OFFSET 9
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#define RTL8366RB_EB_PREIFG_MASK (1 << RTL8366RB_EB_PREIFG_OFFSET)
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#define RTL8366RB_BDTH_SW_MAX 1048512
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2011-01-14 20:19:13 +02:00
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#define RTL8366RB_BDTH_UNIT 64
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2011-01-14 20:19:05 +02:00
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#define RTL8366RB_BDTH_REG_DEFAULT 16383
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/* QOS */
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#define RTL8366RB_QOS_BIT 15
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#define RTL8366RB_QOS_MASK (1 << RTL8366RB_QOS_BIT)
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/* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
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#define RTL8366RB_QOS_DEFAULT_PREIFG 1
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2010-07-01 21:08:39 +03:00
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static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
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{ 0, 0, 4, "IfInOctets" },
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{ 0, 4, 4, "EtherStatsOctets" },
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{ 0, 8, 2, "EtherStatsUnderSizePkts" },
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{ 0, 10, 2, "EtherFragments" },
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{ 0, 12, 2, "EtherStatsPkts64Octets" },
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{ 0, 14, 2, "EtherStatsPkts65to127Octets" },
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{ 0, 16, 2, "EtherStatsPkts128to255Octets" },
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{ 0, 18, 2, "EtherStatsPkts256to511Octets" },
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{ 0, 20, 2, "EtherStatsPkts512to1023Octets" },
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{ 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
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{ 0, 24, 2, "EtherOversizeStats" },
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{ 0, 26, 2, "EtherStatsJabbers" },
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{ 0, 28, 2, "IfInUcastPkts" },
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{ 0, 30, 2, "EtherStatsMulticastPkts" },
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{ 0, 32, 2, "EtherStatsBroadcastPkts" },
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{ 0, 34, 2, "EtherStatsDropEvents" },
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{ 0, 36, 2, "Dot3StatsFCSErrors" },
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{ 0, 38, 2, "Dot3StatsSymbolErrors" },
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{ 0, 40, 2, "Dot3InPauseFrames" },
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{ 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
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{ 0, 44, 4, "IfOutOctets" },
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{ 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
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{ 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
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{ 0, 52, 2, "Dot3sDeferredTransmissions" },
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{ 0, 54, 2, "Dot3StatsLateCollisions" },
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{ 0, 56, 2, "EtherStatsCollisions" },
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{ 0, 58, 2, "Dot3StatsExcessiveCollisions" },
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{ 0, 60, 2, "Dot3OutPauseFrames" },
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{ 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
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{ 0, 64, 2, "Dot1dTpPortInDiscards" },
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{ 0, 66, 2, "IfOutUcastPkts" },
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{ 0, 68, 2, "IfOutMulticastPkts" },
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{ 0, 70, 2, "IfOutBroadcastPkts" },
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2010-02-24 15:39:02 +02:00
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};
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2010-06-26 22:54:11 +03:00
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#define REG_WR(_smi, _reg, _val) \
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do { \
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err = rtl8366_smi_write_reg(_smi, _reg, _val); \
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if (err) \
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return err; \
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} while (0)
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#define REG_RMW(_smi, _reg, _mask, _val) \
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do { \
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err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
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if (err) \
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return err; \
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} while (0)
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2010-06-26 22:53:46 +03:00
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static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
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2010-02-24 15:39:02 +02:00
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{
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int timeout = 10;
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u32 data;
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2010-07-01 21:07:55 +03:00
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rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
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RTL8366RB_CHIP_CTRL_RESET_HW);
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2010-02-24 15:39:02 +02:00
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do {
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msleep(1);
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2010-07-01 21:07:55 +03:00
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if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
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2010-02-24 15:39:02 +02:00
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return -EIO;
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2010-07-01 21:07:55 +03:00
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if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
|
2010-02-24 15:39:02 +02:00
|
|
|
break;
|
|
|
|
} while (--timeout);
|
|
|
|
|
|
|
|
if (!timeout) {
|
|
|
|
printk("Timeout waiting for the switch to reset\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-06-26 22:54:11 +03:00
|
|
|
static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
/* set maximum packet length to 1536 bytes */
|
2010-07-01 21:07:55 +03:00
|
|
|
REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
|
|
|
|
RTL8366RB_SGCR_MAX_LENGTH_1536);
|
2010-06-26 22:54:11 +03:00
|
|
|
|
|
|
|
/* enable all ports */
|
2010-07-01 21:07:55 +03:00
|
|
|
REG_WR(smi, RTL8366RB_PECR, 0);
|
2010-06-26 22:54:11 +03:00
|
|
|
|
2010-08-08 23:15:48 +03:00
|
|
|
/* enable learning for all ports */
|
|
|
|
REG_WR(smi, RTL8366RB_SSCR0, 0);
|
2010-06-26 22:54:11 +03:00
|
|
|
|
2010-08-08 23:15:48 +03:00
|
|
|
/* enable auto ageing for all ports */
|
|
|
|
REG_WR(smi, RTL8366RB_SSCR1, 0);
|
2010-06-26 22:54:11 +03:00
|
|
|
|
2010-07-03 10:29:27 +03:00
|
|
|
/*
|
|
|
|
* discard VLAN tagged packets if the port is not a member of
|
|
|
|
* the VLAN with which the packets is associated.
|
|
|
|
*/
|
|
|
|
REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
|
|
|
|
|
2010-06-26 22:54:11 +03:00
|
|
|
/* don't drop packets whose DA has not been learned */
|
2010-07-01 21:07:55 +03:00
|
|
|
REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
|
2010-06-26 22:54:11 +03:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-06-26 22:53:14 +03:00
|
|
|
static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
|
2010-02-24 15:39:02 +02:00
|
|
|
u32 phy_no, u32 page, u32 addr, u32 *data)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
int ret;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (phy_no > RTL8366RB_PHY_NO_MAX)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (page > RTL8366RB_PHY_PAGE_MAX)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (addr > RTL8366RB_PHY_ADDR_MAX)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
|
|
|
|
RTL8366RB_PHY_CTRL_READ);
|
2010-02-24 15:39:02 +02:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
|
|
|
|
((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
|
|
|
|
(addr & RTL8366RB_PHY_REG_MASK);
|
2010-02-24 15:39:02 +02:00
|
|
|
|
|
|
|
ret = rtl8366_smi_write_reg(smi, reg, 0);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
|
2010-02-24 15:39:02 +02:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-06-26 22:53:14 +03:00
|
|
|
static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
|
2010-02-24 15:39:02 +02:00
|
|
|
u32 phy_no, u32 page, u32 addr, u32 data)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
int ret;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (phy_no > RTL8366RB_PHY_NO_MAX)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (page > RTL8366RB_PHY_PAGE_MAX)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (addr > RTL8366RB_PHY_ADDR_MAX)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
|
|
|
|
RTL8366RB_PHY_CTRL_WRITE);
|
2010-02-24 15:39:02 +02:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
|
|
|
|
((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
|
|
|
|
(addr & RTL8366RB_PHY_REG_MASK);
|
2010-02-24 15:39:02 +02:00
|
|
|
|
|
|
|
ret = rtl8366_smi_write_reg(smi, reg, data);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-07-01 21:08:46 +03:00
|
|
|
static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
|
|
|
|
int port, unsigned long long *val)
|
2010-02-24 15:39:02 +02:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
int err;
|
|
|
|
u32 addr, data;
|
|
|
|
u64 mibvalue;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
addr = RTL8366RB_MIB_COUNTER_BASE +
|
|
|
|
RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
|
2010-02-24 15:39:02 +02:00
|
|
|
rtl8366rb_mib_counters[counter].offset;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Writing access counter address first
|
|
|
|
* then ASIC will prepare 64bits counter wait for being retrived
|
|
|
|
*/
|
|
|
|
data = 0; /* writing data will be discard by ASIC */
|
|
|
|
err = rtl8366_smi_write_reg(smi, addr, data);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
/* read MIB control register */
|
2010-07-01 21:07:55 +03:00
|
|
|
err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
|
2010-02-24 15:39:02 +02:00
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EBUSY;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
mibvalue = 0;
|
|
|
|
for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
|
|
|
|
err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
mibvalue = (mibvalue << 16) | (data & 0xFFFF);
|
|
|
|
}
|
|
|
|
|
|
|
|
*val = mibvalue;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-06-26 22:53:46 +03:00
|
|
|
static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
|
2010-06-26 22:53:38 +03:00
|
|
|
struct rtl8366_vlan_4k *vlan4k)
|
2010-02-24 15:39:02 +02:00
|
|
|
{
|
2010-08-16 22:23:53 +03:00
|
|
|
u32 data[3];
|
2010-02-24 15:39:02 +02:00
|
|
|
int err;
|
2010-08-16 22:23:53 +03:00
|
|
|
int i;
|
2010-02-24 15:39:02 +02:00
|
|
|
|
2010-06-26 22:53:38 +03:00
|
|
|
memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
|
2010-02-24 15:39:02 +02:00
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (vid >= RTL8366RB_NUM_VIDS)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* write VID */
|
2010-08-16 22:23:53 +03:00
|
|
|
err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
|
|
|
|
vid & RTL8366RB_VLAN_VID_MASK);
|
2010-02-24 15:39:02 +02:00
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
/* write table access control word */
|
2010-07-01 21:07:55 +03:00
|
|
|
err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
|
|
|
|
RTL8366RB_TABLE_VLAN_READ_CTRL);
|
2010-02-24 15:39:02 +02:00
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
for (i = 0; i < 3; i++) {
|
|
|
|
err = rtl8366_smi_read_reg(smi,
|
|
|
|
RTL8366RB_VLAN_TABLE_READ_BASE + i,
|
|
|
|
&data[i]);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
}
|
2010-06-26 22:53:38 +03:00
|
|
|
|
2010-02-24 15:39:02 +02:00
|
|
|
vlan4k->vid = vid;
|
2010-08-16 22:23:53 +03:00
|
|
|
vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
|
|
|
|
RTL8366RB_VLAN_UNTAG_MASK;
|
|
|
|
vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
|
|
|
|
vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
|
2010-02-24 15:39:02 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-06-26 22:53:46 +03:00
|
|
|
static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
|
2010-06-26 22:53:38 +03:00
|
|
|
const struct rtl8366_vlan_4k *vlan4k)
|
2010-02-24 15:39:02 +02:00
|
|
|
{
|
2010-08-16 22:23:53 +03:00
|
|
|
u32 data[3];
|
2010-02-24 15:39:02 +02:00
|
|
|
int err;
|
2010-08-16 22:23:53 +03:00
|
|
|
int i;
|
2010-02-24 15:39:02 +02:00
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
|
2011-01-14 20:19:18 +02:00
|
|
|
vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
|
|
|
|
vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
|
2010-07-01 21:07:55 +03:00
|
|
|
vlan4k->fid > RTL8366RB_FIDMAX)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
|
|
|
|
data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
|
|
|
|
((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
|
|
|
|
RTL8366RB_VLAN_UNTAG_SHIFT);
|
|
|
|
data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
|
2010-02-24 15:39:02 +02:00
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
for (i = 0; i < 3; i++) {
|
|
|
|
err = rtl8366_smi_write_reg(smi,
|
|
|
|
RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
|
|
|
|
data[i]);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
}
|
2010-02-24 15:39:02 +02:00
|
|
|
|
|
|
|
/* write table access control word */
|
2010-07-01 21:07:55 +03:00
|
|
|
err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
|
|
|
|
RTL8366RB_TABLE_VLAN_WRITE_CTRL);
|
2010-02-24 15:39:02 +02:00
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2010-06-26 22:53:46 +03:00
|
|
|
static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
|
2010-06-26 22:53:31 +03:00
|
|
|
struct rtl8366_vlan_mc *vlanmc)
|
2010-02-24 15:39:02 +02:00
|
|
|
{
|
2010-08-16 22:23:53 +03:00
|
|
|
u32 data[3];
|
2010-02-24 15:39:02 +02:00
|
|
|
int err;
|
2010-08-16 22:23:53 +03:00
|
|
|
int i;
|
2010-02-24 15:39:02 +02:00
|
|
|
|
2010-06-26 22:53:31 +03:00
|
|
|
memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
|
2010-02-24 15:39:02 +02:00
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (index >= RTL8366RB_NUM_VLANS)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
for (i = 0; i < 3; i++) {
|
|
|
|
err = rtl8366_smi_read_reg(smi,
|
|
|
|
RTL8366RB_VLAN_MC_BASE(index) + i,
|
|
|
|
&data[i]);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
}
|
2010-02-24 15:39:02 +02:00
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
|
|
|
|
vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
|
|
|
|
RTL8366RB_VLAN_PRIORITY_MASK;
|
|
|
|
vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
|
|
|
|
RTL8366RB_VLAN_UNTAG_MASK;
|
|
|
|
vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
|
|
|
|
vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
|
2010-06-26 22:53:31 +03:00
|
|
|
|
2010-02-24 15:39:02 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-06-26 22:53:46 +03:00
|
|
|
static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
|
2010-06-26 22:53:31 +03:00
|
|
|
const struct rtl8366_vlan_mc *vlanmc)
|
2010-02-24 15:39:02 +02:00
|
|
|
{
|
2010-08-16 22:23:53 +03:00
|
|
|
u32 data[3];
|
2010-02-24 15:39:02 +02:00
|
|
|
int err;
|
2010-08-16 22:23:53 +03:00
|
|
|
int i;
|
2010-02-24 15:39:02 +02:00
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (index >= RTL8366RB_NUM_VLANS ||
|
|
|
|
vlanmc->vid >= RTL8366RB_NUM_VIDS ||
|
|
|
|
vlanmc->priority > RTL8366RB_PRIORITYMAX ||
|
2011-01-14 20:19:18 +02:00
|
|
|
vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
|
|
|
|
vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
|
2010-07-01 21:07:55 +03:00
|
|
|
vlanmc->fid > RTL8366RB_FIDMAX)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
|
|
|
|
((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
|
|
|
|
RTL8366RB_VLAN_PRIORITY_SHIFT);
|
|
|
|
data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
|
|
|
|
((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
|
|
|
|
RTL8366RB_VLAN_UNTAG_SHIFT);
|
|
|
|
data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
|
|
|
|
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
|
|
err = rtl8366_smi_write_reg(smi,
|
|
|
|
RTL8366RB_VLAN_MC_BASE(index) + i,
|
|
|
|
data[i]);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
}
|
2010-02-24 15:39:02 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-06-26 22:54:17 +03:00
|
|
|
static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
|
2010-02-24 15:39:02 +02:00
|
|
|
{
|
|
|
|
u32 data;
|
|
|
|
int err;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (port >= RTL8366RB_NUM_PORTS)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
|
2010-02-24 15:39:02 +02:00
|
|
|
&data);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
*val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
|
|
|
|
RTL8366RB_PORT_VLAN_CTRL_MASK;
|
2010-02-24 15:39:02 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2010-06-26 22:54:17 +03:00
|
|
|
static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
|
|
|
|
{
|
2010-07-01 21:07:55 +03:00
|
|
|
if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
|
2010-06-26 22:54:17 +03:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
|
|
|
|
RTL8366RB_PORT_VLAN_CTRL_MASK <<
|
|
|
|
RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
|
|
|
|
(index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
|
|
|
|
RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
|
2010-06-26 22:54:17 +03:00
|
|
|
}
|
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
|
|
|
|
{
|
2010-09-10 02:21:41 +03:00
|
|
|
unsigned max = RTL8366RB_NUM_VLANS;
|
|
|
|
|
|
|
|
if (smi->vlan4k_enabled)
|
|
|
|
max = RTL8366RB_NUM_VIDS - 1;
|
|
|
|
|
|
|
|
if (vlan == 0 || vlan >= max)
|
2010-08-16 22:23:53 +03:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2010-09-10 02:21:41 +03:00
|
|
|
static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)
|
2010-02-24 15:39:02 +02:00
|
|
|
{
|
2010-07-01 21:08:58 +03:00
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
|
|
|
|
(enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
|
2010-02-24 15:39:02 +02:00
|
|
|
}
|
|
|
|
|
2010-09-10 02:21:41 +03:00
|
|
|
static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)
|
2010-02-24 15:39:02 +02:00
|
|
|
{
|
2010-07-01 21:08:58 +03:00
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
|
|
|
|
RTL8366RB_SGCR_EN_VLAN_4KTB,
|
|
|
|
(enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
|
2010-02-24 15:39:02 +02:00
|
|
|
}
|
|
|
|
|
2011-01-14 20:19:41 +02:00
|
|
|
static int rtl8366rb_enable_port(struct rtl8366_smi *smi, int port, int enable)
|
|
|
|
{
|
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, (1 << port),
|
|
|
|
(enable) ? 0 : (1 << port));
|
|
|
|
}
|
|
|
|
|
2010-02-24 15:39:02 +02:00
|
|
|
static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
2010-06-26 22:53:46 +03:00
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
2010-02-24 15:39:02 +02:00
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
|
|
|
|
RTL8366RB_MIB_CTRL_GLOBAL_RESET);
|
2010-02-24 15:39:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
2010-06-26 22:53:46 +03:00
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
2010-02-24 15:39:02 +02:00
|
|
|
u32 data;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
|
2010-02-24 15:39:02 +02:00
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
|
2010-02-24 15:39:02 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
2010-06-26 22:53:46 +03:00
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
2010-02-24 15:39:02 +02:00
|
|
|
|
|
|
|
if (val->value.i >= 6)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
|
|
|
|
RTL8366RB_LED_BLINKRATE_MASK,
|
2010-06-26 22:54:05 +03:00
|
|
|
val->value.i);
|
2010-02-24 15:39:02 +02:00
|
|
|
}
|
|
|
|
|
2010-08-08 23:15:48 +03:00
|
|
|
static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
|
|
|
u32 data;
|
|
|
|
|
|
|
|
rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
|
|
|
|
val->value.i = !data;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
|
|
|
u32 portmask = 0;
|
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
if (!val->value.i)
|
|
|
|
portmask = RTL8366RB_PORT_ALL;
|
|
|
|
|
|
|
|
/* set learning for all ports */
|
|
|
|
REG_WR(smi, RTL8366RB_SSCR0, portmask);
|
|
|
|
|
|
|
|
/* set auto ageing for all ports */
|
|
|
|
REG_WR(smi, RTL8366RB_SSCR1, portmask);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2010-02-24 15:39:02 +02:00
|
|
|
static const char *rtl8366rb_speed_str(unsigned speed)
|
|
|
|
{
|
|
|
|
switch (speed) {
|
|
|
|
case 0:
|
|
|
|
return "10baseT";
|
|
|
|
case 1:
|
|
|
|
return "100baseT";
|
|
|
|
case 2:
|
|
|
|
return "1000baseT";
|
|
|
|
}
|
|
|
|
|
|
|
|
return "unknown";
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
2010-07-01 21:08:26 +03:00
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
2010-02-24 15:39:02 +02:00
|
|
|
u32 len = 0, data = 0;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (val->port_vlan >= RTL8366RB_NUM_PORTS)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-07-01 21:08:26 +03:00
|
|
|
memset(smi->buf, '\0', sizeof(smi->buf));
|
2010-07-01 21:07:55 +03:00
|
|
|
rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
|
2010-02-24 15:39:02 +02:00
|
|
|
(val->port_vlan / 2), &data);
|
|
|
|
|
|
|
|
if (val->port_vlan % 2)
|
|
|
|
data = data >> 8;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
|
2010-07-01 21:08:26 +03:00
|
|
|
len = snprintf(smi->buf, sizeof(smi->buf),
|
2010-06-26 22:52:36 +03:00
|
|
|
"port:%d link:up speed:%s %s-duplex %s%s%s",
|
|
|
|
val->port_vlan,
|
|
|
|
rtl8366rb_speed_str(data &
|
2010-07-01 21:07:55 +03:00
|
|
|
RTL8366RB_PORT_STATUS_SPEED_MASK),
|
|
|
|
(data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
|
2010-06-26 22:52:36 +03:00
|
|
|
"full" : "half",
|
2010-07-01 21:07:55 +03:00
|
|
|
(data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
|
2010-06-26 22:52:36 +03:00
|
|
|
"tx-pause ": "",
|
2010-07-01 21:07:55 +03:00
|
|
|
(data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
|
2010-06-26 22:52:36 +03:00
|
|
|
"rx-pause " : "",
|
2010-07-01 21:07:55 +03:00
|
|
|
(data & RTL8366RB_PORT_STATUS_AN_MASK) ?
|
2010-06-26 22:52:36 +03:00
|
|
|
"nway ": "");
|
|
|
|
} else {
|
2010-07-01 21:08:26 +03:00
|
|
|
len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
|
2010-06-26 22:52:36 +03:00
|
|
|
val->port_vlan);
|
|
|
|
}
|
2010-02-24 15:39:02 +02:00
|
|
|
|
2010-07-01 21:08:26 +03:00
|
|
|
val->value.s = smi->buf;
|
2010-02-24 15:39:02 +02:00
|
|
|
val->len = len;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
2010-06-26 22:53:46 +03:00
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
2010-06-26 22:54:05 +03:00
|
|
|
u32 data;
|
|
|
|
u32 mask;
|
|
|
|
u32 reg;
|
2010-02-24 15:39:02 +02:00
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (val->port_vlan >= RTL8366RB_NUM_PORTS)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
|
|
|
|
reg = RTL8366RB_LED_BLINKRATE_REG;
|
2010-06-26 22:54:05 +03:00
|
|
|
mask = 0xF << 4;
|
|
|
|
data = val->value.i << 4;
|
2010-02-24 15:39:02 +02:00
|
|
|
} else {
|
2010-07-01 21:07:55 +03:00
|
|
|
reg = RTL8366RB_LED_CTRL_REG;
|
2010-06-26 22:54:05 +03:00
|
|
|
mask = 0xF << (val->port_vlan * 4),
|
|
|
|
data = val->value.i << (val->port_vlan * 4);
|
2010-02-24 15:39:02 +02:00
|
|
|
}
|
|
|
|
|
2010-08-15 11:15:09 +03:00
|
|
|
return rtl8366_smi_rmwr(smi, reg, mask, data);
|
2010-02-24 15:39:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
2010-06-26 22:53:46 +03:00
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
2010-02-24 15:39:02 +02:00
|
|
|
u32 data = 0;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
|
2010-02-24 15:39:02 +02:00
|
|
|
val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-01-14 20:19:05 +02:00
|
|
|
static int rtl8366rb_sw_set_port_disable(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
|
|
|
u32 mask, data;
|
|
|
|
|
|
|
|
if (val->port_vlan >= RTL8366RB_NUM_PORTS)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
mask = 1 << val->port_vlan ;
|
|
|
|
if (val->value.i)
|
|
|
|
data = mask;
|
|
|
|
else
|
|
|
|
data = 0;
|
|
|
|
|
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_sw_get_port_disable(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
|
|
|
u32 data;
|
|
|
|
|
|
|
|
if (val->port_vlan >= RTL8366RB_NUM_PORTS)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
rtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data);
|
|
|
|
if (data & (1 << val->port_vlan))
|
|
|
|
val->value.i = 1;
|
|
|
|
else
|
|
|
|
val->value.i = 0;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_sw_set_port_rate_in(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
|
|
|
|
|
|
|
if (val->port_vlan >= RTL8366RB_NUM_PORTS)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
|
2011-01-14 20:19:13 +02:00
|
|
|
val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
|
2011-01-14 20:19:05 +02:00
|
|
|
else
|
|
|
|
val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
|
|
|
|
|
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366RB_IB_REG(val->port_vlan),
|
|
|
|
RTL8366RB_IB_BDTH_MASK | RTL8366RB_IB_PREIFG_MASK,
|
|
|
|
val->value.i |
|
|
|
|
(RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_IB_PREIFG_OFFSET));
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_sw_get_port_rate_in(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
|
|
|
u32 data;
|
|
|
|
|
|
|
|
if (val->port_vlan >= RTL8366RB_NUM_PORTS)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
rtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data);
|
|
|
|
data &= RTL8366RB_IB_BDTH_MASK;
|
|
|
|
if (data < RTL8366RB_IB_BDTH_MASK)
|
|
|
|
data += 1;
|
|
|
|
|
2011-01-14 20:19:13 +02:00
|
|
|
val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
|
2011-01-14 20:19:05 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_sw_set_port_rate_out(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
|
|
|
|
|
|
|
if (val->port_vlan >= RTL8366RB_NUM_PORTS)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
rtl8366_smi_rmwr(smi, RTL8366RB_EB_PREIFG_REG,
|
|
|
|
RTL8366RB_EB_PREIFG_MASK,
|
|
|
|
(RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_EB_PREIFG_OFFSET));
|
|
|
|
|
|
|
|
if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
|
2011-01-14 20:19:13 +02:00
|
|
|
val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
|
2011-01-14 20:19:05 +02:00
|
|
|
else
|
|
|
|
val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
|
|
|
|
|
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366RB_EB_REG(val->port_vlan),
|
|
|
|
RTL8366RB_EB_BDTH_MASK, val->value.i );
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_sw_get_port_rate_out(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
|
|
|
u32 data;
|
|
|
|
|
|
|
|
if (val->port_vlan >= RTL8366RB_NUM_PORTS)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
rtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data);
|
|
|
|
data &= RTL8366RB_EB_BDTH_MASK;
|
|
|
|
if (data < RTL8366RB_EB_BDTH_MASK)
|
|
|
|
data += 1;
|
|
|
|
|
2011-01-14 20:19:13 +02:00
|
|
|
val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
|
2011-01-14 20:19:05 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_sw_set_qos_enable(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
|
|
|
u32 data;
|
|
|
|
|
|
|
|
if (val->value.i)
|
|
|
|
data = RTL8366RB_QOS_MASK;
|
|
|
|
else
|
|
|
|
data = 0;
|
|
|
|
|
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_sw_get_qos_enable(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
|
|
|
u32 data;
|
|
|
|
|
|
|
|
rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
|
|
|
|
if (data & RTL8366RB_QOS_MASK)
|
|
|
|
val->value.i = 1;
|
|
|
|
else
|
|
|
|
val->value.i = 0;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-02-24 15:39:02 +02:00
|
|
|
static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
|
|
|
|
const struct switch_attr *attr,
|
|
|
|
struct switch_val *val)
|
|
|
|
{
|
2010-06-26 22:53:46 +03:00
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
2010-02-24 15:39:02 +02:00
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
if (val->port_vlan >= RTL8366RB_NUM_PORTS)
|
2010-02-24 15:39:02 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
|
|
|
|
RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
|
2010-02-24 15:39:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
|
|
|
|
{
|
2010-06-26 22:53:46 +03:00
|
|
|
struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
|
2010-02-24 15:39:02 +02:00
|
|
|
int err;
|
|
|
|
|
2010-06-26 22:53:46 +03:00
|
|
|
err = rtl8366rb_reset_chip(smi);
|
2010-02-24 15:39:02 +02:00
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2010-06-26 22:54:11 +03:00
|
|
|
err = rtl8366rb_hw_init(smi);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2010-07-01 21:08:19 +03:00
|
|
|
return rtl8366_reset_vlan(smi);
|
2010-02-24 15:39:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct switch_attr rtl8366rb_globals[] = {
|
|
|
|
{
|
2010-08-08 23:15:48 +03:00
|
|
|
.type = SWITCH_TYPE_INT,
|
|
|
|
.name = "enable_learning",
|
|
|
|
.description = "Enable learning, enable aging",
|
|
|
|
.set = rtl8366rb_sw_set_learning_enable,
|
|
|
|
.get = rtl8366rb_sw_get_learning_enable,
|
|
|
|
.max = 1
|
|
|
|
}, {
|
2010-02-24 15:39:02 +02:00
|
|
|
.type = SWITCH_TYPE_INT,
|
|
|
|
.name = "enable_vlan",
|
|
|
|
.description = "Enable VLAN mode",
|
2010-09-10 02:21:41 +03:00
|
|
|
.set = rtl8366_sw_set_vlan_enable,
|
|
|
|
.get = rtl8366_sw_get_vlan_enable,
|
2010-02-24 15:39:02 +02:00
|
|
|
.max = 1,
|
|
|
|
.ofs = 1
|
|
|
|
}, {
|
|
|
|
.type = SWITCH_TYPE_INT,
|
|
|
|
.name = "enable_vlan4k",
|
|
|
|
.description = "Enable VLAN 4K mode",
|
2010-09-10 02:21:41 +03:00
|
|
|
.set = rtl8366_sw_set_vlan_enable,
|
|
|
|
.get = rtl8366_sw_get_vlan_enable,
|
2010-02-24 15:39:02 +02:00
|
|
|
.max = 1,
|
|
|
|
.ofs = 2
|
|
|
|
}, {
|
2010-08-16 22:23:53 +03:00
|
|
|
.type = SWITCH_TYPE_NOVAL,
|
2010-02-24 15:39:02 +02:00
|
|
|
.name = "reset_mibs",
|
|
|
|
.description = "Reset all MIB counters",
|
|
|
|
.set = rtl8366rb_sw_reset_mibs,
|
|
|
|
}, {
|
|
|
|
.type = SWITCH_TYPE_INT,
|
|
|
|
.name = "blinkrate",
|
|
|
|
.description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
|
|
|
|
" 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
|
|
|
|
.set = rtl8366rb_sw_set_blinkrate,
|
|
|
|
.get = rtl8366rb_sw_get_blinkrate,
|
|
|
|
.max = 5
|
2011-01-14 20:19:05 +02:00
|
|
|
}, {
|
|
|
|
.type = SWITCH_TYPE_INT,
|
|
|
|
.name = "enable_qos",
|
|
|
|
.description = "Enable QOS",
|
|
|
|
.set = rtl8366rb_sw_set_qos_enable,
|
|
|
|
.get = rtl8366rb_sw_get_qos_enable,
|
|
|
|
.max = 1
|
2010-02-24 15:39:02 +02:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct switch_attr rtl8366rb_port[] = {
|
|
|
|
{
|
|
|
|
.type = SWITCH_TYPE_STRING,
|
|
|
|
.name = "link",
|
|
|
|
.description = "Get port link information",
|
|
|
|
.max = 1,
|
|
|
|
.set = NULL,
|
|
|
|
.get = rtl8366rb_sw_get_port_link,
|
|
|
|
}, {
|
2010-08-16 22:23:53 +03:00
|
|
|
.type = SWITCH_TYPE_NOVAL,
|
2010-02-24 15:39:02 +02:00
|
|
|
.name = "reset_mib",
|
|
|
|
.description = "Reset single port MIB counters",
|
|
|
|
.set = rtl8366rb_sw_reset_port_mibs,
|
|
|
|
}, {
|
|
|
|
.type = SWITCH_TYPE_STRING,
|
|
|
|
.name = "mib",
|
|
|
|
.description = "Get MIB counters for port",
|
|
|
|
.max = 33,
|
|
|
|
.set = NULL,
|
2010-08-16 22:23:53 +03:00
|
|
|
.get = rtl8366_sw_get_port_mib,
|
2010-02-24 15:39:02 +02:00
|
|
|
}, {
|
|
|
|
.type = SWITCH_TYPE_INT,
|
|
|
|
.name = "led",
|
|
|
|
.description = "Get/Set port group (0 - 3) led mode (0 - 15)",
|
|
|
|
.max = 15,
|
|
|
|
.set = rtl8366rb_sw_set_port_led,
|
|
|
|
.get = rtl8366rb_sw_get_port_led,
|
2011-01-14 20:19:05 +02:00
|
|
|
}, {
|
|
|
|
.type = SWITCH_TYPE_INT,
|
|
|
|
.name = "disable",
|
|
|
|
.description = "Get/Set port state (enabled or disabled)",
|
|
|
|
.max = 1,
|
|
|
|
.set = rtl8366rb_sw_set_port_disable,
|
|
|
|
.get = rtl8366rb_sw_get_port_disable,
|
|
|
|
}, {
|
|
|
|
.type = SWITCH_TYPE_INT,
|
|
|
|
.name = "rate_in",
|
|
|
|
.description = "Get/Set port ingress (incoming) bandwidth limit in kbps",
|
|
|
|
.max = RTL8366RB_BDTH_SW_MAX,
|
|
|
|
.set = rtl8366rb_sw_set_port_rate_in,
|
|
|
|
.get = rtl8366rb_sw_get_port_rate_in,
|
|
|
|
}, {
|
|
|
|
.type = SWITCH_TYPE_INT,
|
|
|
|
.name = "rate_out",
|
|
|
|
.description = "Get/Set port egress (outgoing) bandwidth limit in kbps",
|
|
|
|
.max = RTL8366RB_BDTH_SW_MAX,
|
|
|
|
.set = rtl8366rb_sw_set_port_rate_out,
|
|
|
|
.get = rtl8366rb_sw_get_port_rate_out,
|
2010-02-24 15:39:02 +02:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct switch_attr rtl8366rb_vlan[] = {
|
|
|
|
{
|
|
|
|
.type = SWITCH_TYPE_STRING,
|
|
|
|
.name = "info",
|
|
|
|
.description = "Get vlan information",
|
|
|
|
.max = 1,
|
|
|
|
.set = NULL,
|
2010-08-16 22:23:53 +03:00
|
|
|
.get = rtl8366_sw_get_vlan_info,
|
2011-01-14 20:19:13 +02:00
|
|
|
}, {
|
|
|
|
.type = SWITCH_TYPE_INT,
|
|
|
|
.name = "fid",
|
|
|
|
.description = "Get/Set vlan FID",
|
|
|
|
.max = RTL8366RB_FIDMAX,
|
|
|
|
.set = rtl8366_sw_set_vlan_fid,
|
|
|
|
.get = rtl8366_sw_get_vlan_fid,
|
2010-02-24 15:39:02 +02:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
static const struct switch_dev_ops rtl8366_ops = {
|
2010-02-24 15:39:02 +02:00
|
|
|
.attr_global = {
|
|
|
|
.attr = rtl8366rb_globals,
|
|
|
|
.n_attr = ARRAY_SIZE(rtl8366rb_globals),
|
|
|
|
},
|
|
|
|
.attr_port = {
|
|
|
|
.attr = rtl8366rb_port,
|
|
|
|
.n_attr = ARRAY_SIZE(rtl8366rb_port),
|
|
|
|
},
|
|
|
|
.attr_vlan = {
|
|
|
|
.attr = rtl8366rb_vlan,
|
|
|
|
.n_attr = ARRAY_SIZE(rtl8366rb_vlan),
|
|
|
|
},
|
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
.get_vlan_ports = rtl8366_sw_get_vlan_ports,
|
|
|
|
.set_vlan_ports = rtl8366_sw_set_vlan_ports,
|
|
|
|
.get_port_pvid = rtl8366_sw_get_port_pvid,
|
|
|
|
.set_port_pvid = rtl8366_sw_set_port_pvid,
|
2010-02-24 15:39:02 +02:00
|
|
|
.reset_switch = rtl8366rb_sw_reset_switch,
|
|
|
|
};
|
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
|
2010-02-24 15:39:02 +02:00
|
|
|
{
|
2010-08-16 22:23:53 +03:00
|
|
|
struct switch_dev *dev = &smi->sw_dev;
|
2010-02-24 15:39:02 +02:00
|
|
|
int err;
|
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
dev->name = "RTL8366RB";
|
|
|
|
dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
|
|
|
|
dev->ports = RTL8366RB_NUM_PORTS;
|
2010-09-10 02:21:41 +03:00
|
|
|
dev->vlans = RTL8366RB_NUM_VIDS;
|
2010-08-16 22:23:53 +03:00
|
|
|
dev->ops = &rtl8366_ops;
|
|
|
|
dev->devname = dev_name(smi->parent);
|
2010-02-24 15:39:02 +02:00
|
|
|
|
|
|
|
err = register_switch(dev, NULL);
|
|
|
|
if (err)
|
2010-08-16 22:23:53 +03:00
|
|
|
dev_err(smi->parent, "switch registration failed\n");
|
2010-02-24 15:39:02 +02:00
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
|
2010-02-24 15:39:02 +02:00
|
|
|
{
|
2010-08-16 22:23:53 +03:00
|
|
|
unregister_switch(&smi->sw_dev);
|
2010-02-24 15:39:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
|
|
|
|
{
|
2010-06-26 22:53:14 +03:00
|
|
|
struct rtl8366_smi *smi = bus->priv;
|
2010-02-24 15:39:02 +02:00
|
|
|
u32 val = 0;
|
|
|
|
int err;
|
|
|
|
|
2010-06-26 22:53:14 +03:00
|
|
|
err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
|
2010-02-24 15:39:02 +02:00
|
|
|
if (err)
|
|
|
|
return 0xffff;
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
|
|
|
|
{
|
2010-06-26 22:53:14 +03:00
|
|
|
struct rtl8366_smi *smi = bus->priv;
|
2010-02-24 15:39:02 +02:00
|
|
|
u32 t;
|
|
|
|
int err;
|
|
|
|
|
2010-06-26 22:53:14 +03:00
|
|
|
err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
|
2010-02-24 15:39:02 +02:00
|
|
|
/* flush write */
|
2010-06-26 22:53:14 +03:00
|
|
|
(void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
|
2010-02-24 15:39:02 +02:00
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
|
|
|
|
{
|
|
|
|
return (bus->read == rtl8366rb_mii_read &&
|
|
|
|
bus->write == rtl8366rb_mii_write);
|
|
|
|
}
|
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
static int rtl8366rb_setup(struct rtl8366_smi *smi)
|
2010-02-24 15:39:02 +02:00
|
|
|
{
|
2010-06-26 22:52:55 +03:00
|
|
|
int ret;
|
|
|
|
|
2010-06-26 22:53:46 +03:00
|
|
|
ret = rtl8366rb_reset_chip(smi);
|
2010-06-26 22:52:55 +03:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2010-06-26 22:54:11 +03:00
|
|
|
ret = rtl8366rb_hw_init(smi);
|
|
|
|
return ret;
|
2010-06-26 22:52:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_detect(struct rtl8366_smi *smi)
|
|
|
|
{
|
2010-02-24 15:39:02 +02:00
|
|
|
u32 chip_id = 0;
|
|
|
|
u32 chip_ver = 0;
|
|
|
|
int ret;
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
|
2010-02-24 15:39:02 +02:00
|
|
|
if (ret) {
|
2010-06-26 22:52:55 +03:00
|
|
|
dev_err(smi->parent, "unable to read chip id\n");
|
2010-02-24 15:39:02 +02:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (chip_id) {
|
2010-07-01 21:07:55 +03:00
|
|
|
case RTL8366RB_CHIP_ID_8366:
|
2010-02-24 15:39:02 +02:00
|
|
|
break;
|
|
|
|
default:
|
2010-06-26 22:52:55 +03:00
|
|
|
dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
|
2010-02-24 15:39:02 +02:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
|
2010-02-24 15:39:02 +02:00
|
|
|
&chip_ver);
|
|
|
|
if (ret) {
|
2010-06-26 22:52:55 +03:00
|
|
|
dev_err(smi->parent, "unable to read chip version\n");
|
2010-02-24 15:39:02 +02:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-06-26 22:52:55 +03:00
|
|
|
dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
|
2010-07-01 21:07:55 +03:00
|
|
|
chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
|
2010-02-24 15:39:02 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-06-26 22:52:55 +03:00
|
|
|
static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
|
|
|
|
.detect = rtl8366rb_detect,
|
2010-08-16 22:23:53 +03:00
|
|
|
.setup = rtl8366rb_setup,
|
|
|
|
|
2010-06-26 22:53:05 +03:00
|
|
|
.mii_read = rtl8366rb_mii_read,
|
|
|
|
.mii_write = rtl8366rb_mii_write,
|
2010-07-01 21:08:03 +03:00
|
|
|
|
|
|
|
.get_vlan_mc = rtl8366rb_get_vlan_mc,
|
|
|
|
.set_vlan_mc = rtl8366rb_set_vlan_mc,
|
|
|
|
.get_vlan_4k = rtl8366rb_get_vlan_4k,
|
|
|
|
.set_vlan_4k = rtl8366rb_set_vlan_4k,
|
|
|
|
.get_mc_index = rtl8366rb_get_mc_index,
|
|
|
|
.set_mc_index = rtl8366rb_set_mc_index,
|
2010-07-01 21:08:46 +03:00
|
|
|
.get_mib_counter = rtl8366rb_get_mib_counter,
|
2010-08-16 22:23:53 +03:00
|
|
|
.is_vlan_valid = rtl8366rb_is_vlan_valid,
|
2010-09-10 02:21:41 +03:00
|
|
|
.enable_vlan = rtl8366rb_enable_vlan,
|
|
|
|
.enable_vlan4k = rtl8366rb_enable_vlan4k,
|
2011-01-14 20:19:41 +02:00
|
|
|
.enable_port = rtl8366rb_enable_port,
|
2010-06-26 22:52:55 +03:00
|
|
|
};
|
|
|
|
|
2011-01-14 20:19:09 +02:00
|
|
|
static int __devinit rtl8366rb_probe(struct platform_device *pdev)
|
2010-02-24 15:39:02 +02:00
|
|
|
{
|
|
|
|
static int rtl8366_smi_version_printed;
|
|
|
|
struct rtl8366rb_platform_data *pdata;
|
|
|
|
struct rtl8366_smi *smi;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
if (!rtl8366_smi_version_printed++)
|
2010-07-01 21:07:55 +03:00
|
|
|
printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
|
|
|
|
" version " RTL8366RB_DRIVER_VER"\n");
|
2010-02-24 15:39:02 +02:00
|
|
|
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
|
|
if (!pdata) {
|
|
|
|
dev_err(&pdev->dev, "no platform data specified\n");
|
|
|
|
err = -EINVAL;
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
smi = rtl8366_smi_alloc(&pdev->dev);
|
|
|
|
if (!smi) {
|
2010-02-24 15:39:02 +02:00
|
|
|
err = -ENOMEM;
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
smi->gpio_sda = pdata->gpio_sda;
|
|
|
|
smi->gpio_sck = pdata->gpio_sck;
|
2010-06-26 22:52:55 +03:00
|
|
|
smi->ops = &rtl8366rb_smi_ops;
|
2010-07-01 21:08:11 +03:00
|
|
|
smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
|
|
|
|
smi->num_ports = RTL8366RB_NUM_PORTS;
|
|
|
|
smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
|
2010-07-01 21:08:46 +03:00
|
|
|
smi->mib_counters = rtl8366rb_mib_counters;
|
|
|
|
smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
|
2010-02-24 15:39:02 +02:00
|
|
|
|
|
|
|
err = rtl8366_smi_init(smi);
|
|
|
|
if (err)
|
2010-08-16 22:23:53 +03:00
|
|
|
goto err_free_smi;
|
2010-02-24 15:39:02 +02:00
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
platform_set_drvdata(pdev, smi);
|
2010-02-24 15:39:02 +02:00
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
err = rtl8366rb_switch_init(smi);
|
2010-02-24 15:39:02 +02:00
|
|
|
if (err)
|
2010-06-26 22:53:05 +03:00
|
|
|
goto err_clear_drvdata;
|
2010-02-24 15:39:02 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_clear_drvdata:
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
rtl8366_smi_cleanup(smi);
|
2010-08-16 22:23:53 +03:00
|
|
|
err_free_smi:
|
|
|
|
kfree(smi);
|
2010-02-24 15:39:02 +02:00
|
|
|
err_out:
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_phy_config_init(struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
if (!rtl8366rb_mii_bus_match(phydev->bus))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
|
|
|
|
{
|
2010-10-27 14:34:36 +03:00
|
|
|
/* phy 4 might be connected to a second mac, allow aneg config */
|
|
|
|
if (phydev->addr == RTL8366RB_PHY_WAN)
|
|
|
|
return genphy_config_aneg(phydev);
|
|
|
|
|
2010-02-24 15:39:02 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct phy_driver rtl8366rb_phy_driver = {
|
|
|
|
.phy_id = 0x001cc960,
|
|
|
|
.name = "Realtek RTL8366RB",
|
|
|
|
.phy_id_mask = 0x1ffffff0,
|
|
|
|
.features = PHY_GBIT_FEATURES,
|
|
|
|
.config_aneg = rtl8366rb_phy_config_aneg,
|
|
|
|
.config_init = rtl8366rb_phy_config_init,
|
|
|
|
.read_status = genphy_read_status,
|
|
|
|
.driver = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __devexit rtl8366rb_remove(struct platform_device *pdev)
|
|
|
|
{
|
2010-08-16 22:23:53 +03:00
|
|
|
struct rtl8366_smi *smi = platform_get_drvdata(pdev);
|
2010-02-24 15:39:02 +02:00
|
|
|
|
2010-08-16 22:23:53 +03:00
|
|
|
if (smi) {
|
|
|
|
rtl8366rb_switch_cleanup(smi);
|
2010-02-24 15:39:02 +02:00
|
|
|
platform_set_drvdata(pdev, NULL);
|
2010-08-16 22:23:53 +03:00
|
|
|
rtl8366_smi_cleanup(smi);
|
|
|
|
kfree(smi);
|
2010-02-24 15:39:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver rtl8366rb_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = RTL8366RB_DRIVER_NAME,
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
},
|
|
|
|
.probe = rtl8366rb_probe,
|
|
|
|
.remove = __devexit_p(rtl8366rb_remove),
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init rtl8366rb_module_init(void)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
ret = platform_driver_register(&rtl8366rb_driver);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = phy_driver_register(&rtl8366rb_phy_driver);
|
|
|
|
if (ret)
|
|
|
|
goto err_platform_unregister;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_platform_unregister:
|
|
|
|
platform_driver_unregister(&rtl8366rb_driver);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
module_init(rtl8366rb_module_init);
|
|
|
|
|
|
|
|
static void __exit rtl8366rb_module_exit(void)
|
|
|
|
{
|
|
|
|
phy_driver_unregister(&rtl8366rb_phy_driver);
|
|
|
|
platform_driver_unregister(&rtl8366rb_driver);
|
|
|
|
}
|
|
|
|
module_exit(rtl8366rb_module_exit);
|
|
|
|
|
2010-07-01 21:07:55 +03:00
|
|
|
MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
|
|
|
|
MODULE_VERSION(RTL8366RB_DRIVER_VER);
|
2010-02-24 15:39:02 +02:00
|
|
|
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
|
|
|
|
MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
|
2011-01-14 20:19:05 +02:00
|
|
|
MODULE_AUTHOR("Roman Yeryomin <roman@advem.lv>");
|
2010-02-24 15:39:02 +02:00
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
|