mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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234 lines
11 KiB
C
234 lines
11 KiB
C
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/*
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* Copyright (c) 2008 Daniel Mueller (daniel@danm.de)
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* Copyright (c) 2000 Theo de Raadt
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* Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Effort sponsored in part by the Defense Advanced Research Projects
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* Agency (DARPA) and Air Force Research Laboratory, Air Force
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* Materiel Command, USAF, under agreement number F30602-01-2-0537.
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*
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*/
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/*
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* Register definitions for 5601 BlueSteel Networks Ubiquitous Broadband
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* Security "uBSec" chip. Definitions from revision 2.8 of the product
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* datasheet.
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*/
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#define BS_BAR 0x10 /* DMA base address register */
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#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */
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#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */
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#define UBS_PCI_RTY_SHIFT 8
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#define UBS_PCI_RTY_MASK 0xff
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#define UBS_PCI_RTY(misc) \
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(((misc) >> UBS_PCI_RTY_SHIFT) & UBS_PCI_RTY_MASK)
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#define UBS_PCI_TOUT_SHIFT 0
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#define UBS_PCI_TOUT_MASK 0xff
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#define UBS_PCI_TOUT(misc) \
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(((misc) >> PCI_TOUT_SHIFT) & PCI_TOUT_MASK)
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/*
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* DMA Control & Status Registers (offset from BS_BAR)
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*/
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#define BS_MCR1 0x20 /* DMA Master Command Record 1 */
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#define BS_CTRL 0x24 /* DMA Control */
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#define BS_STAT 0x28 /* DMA Status */
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#define BS_ERR 0x2c /* DMA Error Address */
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#define BS_DEV_ID 0x34 /* IPSec Device ID */
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/* BS_CTRL - DMA Control */
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#define BS_CTRL_RESET 0x80000000 /* hardware reset, 5805/5820 */
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#define BS_CTRL_MCR2INT 0x40000000 /* enable intr MCR for MCR2 */
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#define BS_CTRL_MCR1INT 0x20000000 /* enable intr MCR for MCR1 */
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#define BS_CTRL_OFM 0x10000000 /* Output fragment mode */
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#define BS_CTRL_BE32 0x08000000 /* big-endian, 32bit bytes */
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#define BS_CTRL_BE64 0x04000000 /* big-endian, 64bit bytes */
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#define BS_CTRL_DMAERR 0x02000000 /* enable intr DMA error */
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#define BS_CTRL_RNG_M 0x01800000 /* RNG mode */
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#define BS_CTRL_RNG_1 0x00000000 /* 1bit rn/one slow clock */
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#define BS_CTRL_RNG_4 0x00800000 /* 1bit rn/four slow clocks */
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#define BS_CTRL_RNG_8 0x01000000 /* 1bit rn/eight slow clocks */
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#define BS_CTRL_RNG_16 0x01800000 /* 1bit rn/16 slow clocks */
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#define BS_CTRL_SWNORM 0x00400000 /* 582[01], sw normalization */
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#define BS_CTRL_FRAG_M 0x0000ffff /* output fragment size mask */
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#define BS_CTRL_LITTLE_ENDIAN (BS_CTRL_BE32 | BS_CTRL_BE64)
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/* BS_STAT - DMA Status */
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#define BS_STAT_MCR1_BUSY 0x80000000 /* MCR1 is busy */
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#define BS_STAT_MCR1_FULL 0x40000000 /* MCR1 is full */
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#define BS_STAT_MCR1_DONE 0x20000000 /* MCR1 is done */
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#define BS_STAT_DMAERR 0x10000000 /* DMA error */
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#define BS_STAT_MCR2_FULL 0x08000000 /* MCR2 is full */
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#define BS_STAT_MCR2_DONE 0x04000000 /* MCR2 is done */
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#define BS_STAT_MCR1_ALLEMPTY 0x02000000 /* 5821, MCR1 is empty */
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#define BS_STAT_MCR2_ALLEMPTY 0x01000000 /* 5821, MCR2 is empty */
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/* BS_ERR - DMA Error Address */
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#define BS_ERR_ADDR 0xfffffffc /* error address mask */
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#define BS_ERR_READ 0x00000002 /* fault was on read */
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struct ubsec_pktctx {
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u_int32_t pc_deskey[6]; /* 3DES key */
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u_int32_t pc_hminner[5]; /* hmac inner state */
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u_int32_t pc_hmouter[5]; /* hmac outer state */
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u_int32_t pc_iv[2]; /* [3]DES iv */
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u_int16_t pc_flags; /* flags, below */
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u_int16_t pc_offset; /* crypto offset */
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} __attribute__ ((packed));
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#define UBS_PKTCTX_ENC_3DES 0x8000 /* use 3des */
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#define UBS_PKTCTX_ENC_AES 0x8000 /* use aes */
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#define UBS_PKTCTX_ENC_NONE 0x0000 /* no encryption */
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#define UBS_PKTCTX_INBOUND 0x4000 /* inbound packet */
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#define UBS_PKTCTX_AUTH 0x3000 /* authentication mask */
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#define UBS_PKTCTX_AUTH_NONE 0x0000 /* no authentication */
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#define UBS_PKTCTX_AUTH_MD5 0x1000 /* use hmac-md5 */
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#define UBS_PKTCTX_AUTH_SHA1 0x2000 /* use hmac-sha1 */
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#define UBS_PKTCTX_AES128 0x0 /* AES 128bit keys */
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#define UBS_PKTCTX_AES192 0x100 /* AES 192bit keys */
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#define UBS_PKTCTX_AES256 0x200 /* AES 256bit keys */
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struct ubsec_pktctx_des {
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volatile u_int16_t pc_len; /* length of ctx struct */
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volatile u_int16_t pc_type; /* context type */
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volatile u_int16_t pc_flags; /* flags, same as above */
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volatile u_int16_t pc_offset; /* crypto/auth offset */
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volatile u_int32_t pc_deskey[6]; /* 3DES key */
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volatile u_int32_t pc_iv[2]; /* [3]DES iv */
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volatile u_int32_t pc_hminner[5]; /* hmac inner state */
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volatile u_int32_t pc_hmouter[5]; /* hmac outer state */
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} __attribute__ ((packed));
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struct ubsec_pktctx_aes128 {
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volatile u_int16_t pc_len; /* length of ctx struct */
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volatile u_int16_t pc_type; /* context type */
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volatile u_int16_t pc_flags; /* flags, same as above */
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volatile u_int16_t pc_offset; /* crypto/auth offset */
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volatile u_int32_t pc_aeskey[4]; /* AES 128bit key */
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volatile u_int32_t pc_iv[4]; /* AES iv */
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volatile u_int32_t pc_hminner[5]; /* hmac inner state */
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volatile u_int32_t pc_hmouter[5]; /* hmac outer state */
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} __attribute__ ((packed));
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struct ubsec_pktctx_aes192 {
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volatile u_int16_t pc_len; /* length of ctx struct */
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volatile u_int16_t pc_type; /* context type */
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volatile u_int16_t pc_flags; /* flags, same as above */
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volatile u_int16_t pc_offset; /* crypto/auth offset */
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volatile u_int32_t pc_aeskey[6]; /* AES 192bit key */
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volatile u_int32_t pc_iv[4]; /* AES iv */
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volatile u_int32_t pc_hminner[5]; /* hmac inner state */
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volatile u_int32_t pc_hmouter[5]; /* hmac outer state */
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} __attribute__ ((packed));
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struct ubsec_pktctx_aes256 {
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volatile u_int16_t pc_len; /* length of ctx struct */
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volatile u_int16_t pc_type; /* context type */
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volatile u_int16_t pc_flags; /* flags, same as above */
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volatile u_int16_t pc_offset; /* crypto/auth offset */
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volatile u_int32_t pc_aeskey[8]; /* AES 256bit key */
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volatile u_int32_t pc_iv[4]; /* AES iv */
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volatile u_int32_t pc_hminner[5]; /* hmac inner state */
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volatile u_int32_t pc_hmouter[5]; /* hmac outer state */
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} __attribute__ ((packed));
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#define UBS_PKTCTX_TYPE_IPSEC_DES 0x0000
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#define UBS_PKTCTX_TYPE_IPSEC_AES 0x0040
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struct ubsec_pktbuf {
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volatile u_int32_t pb_addr; /* address of buffer start */
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volatile u_int32_t pb_next; /* pointer to next pktbuf */
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volatile u_int32_t pb_len; /* packet length */
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} __attribute__ ((packed));
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#define UBS_PKTBUF_LEN 0x0000ffff /* length mask */
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struct ubsec_mcr {
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volatile u_int16_t mcr_pkts; /* #pkts in this mcr */
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volatile u_int16_t mcr_flags; /* mcr flags (below) */
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volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */
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struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */
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volatile u_int16_t mcr_reserved;
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volatile u_int16_t mcr_pktlen;
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struct ubsec_pktbuf mcr_opktbuf; /* output chain header */
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} __attribute__ ((packed));
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struct ubsec_mcr_add {
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volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */
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struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */
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volatile u_int16_t mcr_reserved;
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volatile u_int16_t mcr_pktlen;
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struct ubsec_pktbuf mcr_opktbuf; /* output chain header */
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} __attribute__ ((packed));
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#define UBS_MCR_DONE 0x0001 /* mcr has been processed */
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#define UBS_MCR_ERROR 0x0002 /* error in processing */
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#define UBS_MCR_ERRORCODE 0xff00 /* error type */
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struct ubsec_ctx_keyop {
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volatile u_int16_t ctx_len; /* command length */
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volatile u_int16_t ctx_op; /* operation code */
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volatile u_int8_t ctx_pad[60]; /* padding */
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} __attribute__ ((packed));
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#define UBS_CTXOP_DHPKGEN 0x01 /* dh public key generation */
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#define UBS_CTXOP_DHSSGEN 0x02 /* dh shared secret gen. */
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#define UBS_CTXOP_RSAPUB 0x03 /* rsa public key op */
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#define UBS_CTXOP_RSAPRIV 0x04 /* rsa private key op */
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#define UBS_CTXOP_DSASIGN 0x05 /* dsa signing op */
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#define UBS_CTXOP_DSAVRFY 0x06 /* dsa verification */
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#define UBS_CTXOP_RNGBYPASS 0x41 /* rng direct test mode */
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#define UBS_CTXOP_RNGSHA1 0x42 /* rng sha1 test mode */
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#define UBS_CTXOP_MODADD 0x43 /* modular addition */
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#define UBS_CTXOP_MODSUB 0x44 /* modular subtraction */
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#define UBS_CTXOP_MODMUL 0x45 /* modular multiplication */
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#define UBS_CTXOP_MODRED 0x46 /* modular reduction */
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#define UBS_CTXOP_MODEXP 0x47 /* modular exponentiation */
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#define UBS_CTXOP_MODINV 0x48 /* modular inverse */
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struct ubsec_ctx_rngbypass {
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volatile u_int16_t rbp_len; /* command length, 64 */
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volatile u_int16_t rbp_op; /* rng bypass, 0x41 */
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volatile u_int8_t rbp_pad[60]; /* padding */
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} __attribute__ ((packed));
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/* modexp: C = (M ^ E) mod N */
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struct ubsec_ctx_modexp {
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volatile u_int16_t me_len; /* command length */
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volatile u_int16_t me_op; /* modexp, 0x47 */
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volatile u_int16_t me_E_len; /* E (bits) */
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volatile u_int16_t me_N_len; /* N (bits) */
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u_int8_t me_N[2048/8]; /* N */
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} __attribute__ ((packed));
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struct ubsec_ctx_rsapriv {
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volatile u_int16_t rpr_len; /* command length */
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volatile u_int16_t rpr_op; /* rsaprivate, 0x04 */
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volatile u_int16_t rpr_q_len; /* q (bits) */
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volatile u_int16_t rpr_p_len; /* p (bits) */
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u_int8_t rpr_buf[5 * 1024 / 8]; /* parameters: */
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/* p, q, dp, dq, pinv */
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} __attribute__ ((packed));
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