mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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118 lines
2.8 KiB
C
118 lines
2.8 KiB
C
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/*
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* Copyright 2004, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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* $Id$
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/serial_reg.h>
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#include <linux/interrupt.h>
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#include <asm/addrspace.h>
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#include <asm/io.h>
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#include <asm/time.h>
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#include <typedefs.h>
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#include <bcmnvram.h>
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#include <sbconfig.h>
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#include <sbextif.h>
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#include <sbutils.h>
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#include <sbmips.h>
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/* Global SB handle */
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extern void *bcm947xx_sbh;
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extern spinlock_t bcm947xx_sbh_lock;
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/* Convenience */
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#define sbh bcm947xx_sbh
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#define sbh_lock bcm947xx_sbh_lock
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extern int panic_timeout;
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static int watchdog = 0;
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static u8 *mcr = NULL;
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void __init
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bcm947xx_time_init(void)
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{
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unsigned int hz;
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extifregs_t *eir;
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/*
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* Use deterministic values for initial counter interrupt
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* so that calibrate delay avoids encountering a counter wrap.
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*/
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write_c0_count(0);
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write_c0_compare(0xffff);
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if (!(hz = sb_mips_clock(sbh)))
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hz = 100000000;
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printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
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(hz + 500000) / 1000000);
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/* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
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mips_hpt_frequency = hz / 2;
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/* Set watchdog interval in ms */
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watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
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/* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
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if (watchdog > 0) {
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if (watchdog < 3000)
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watchdog = 3000;
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}
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/* Set panic timeout in seconds */
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panic_timeout = watchdog / 1000;
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/* Setup blink */
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if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
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sbconfig_t *sb = (sbconfig_t *)((unsigned int) eir + SBCONFIGOFF);
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unsigned long base = EXTIF_CFGIF_BASE(sb_base(readl(&sb->sbadmatch1)));
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mcr = (u8 *) ioremap_nocache(base + UART_MCR, 1);
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}
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}
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static void
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bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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/* Generic MIPS timer code */
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timer_interrupt(irq, dev_id, regs);
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/* Set the watchdog timer to reset after the specified number of ms */
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if (watchdog > 0)
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sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
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#ifdef CONFIG_HWSIM
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(*((int *)0xa0000f1c))++;
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#else
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/* Blink one of the LEDs in the external UART */
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if (mcr && !(jiffies % (HZ/2)))
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writeb(readb(mcr) ^ UART_MCR_OUT2, mcr);
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#endif
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}
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static struct irqaction bcm947xx_timer_irqaction = {
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bcm947xx_timer_interrupt,
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SA_INTERRUPT,
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0,
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"timer",
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NULL,
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NULL
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};
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void __init
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bcm947xx_timer_setup(struct irqaction *irq)
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{
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/* Enable the timer interrupt */
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setup_irq(7, &bcm947xx_timer_irqaction);
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}
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