mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-12 05:00:36 +02:00
823 lines
24 KiB
C
823 lines
24 KiB
C
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/*
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* linux/arch/mips/jz4750d/dma.c
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*
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* Support functions for the JZ4750D internal DMA channels.
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* No-descriptor transfer only.
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* Descriptor transfer should also call jz_request_dma() to get a free
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* channel and call jz_free_dma() to free the channel. And driver should
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* build the DMA descriptor and setup the DMA channel by itself.
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*
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* Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/soundcard.h>
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#include <asm/system.h>
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#include <asm/addrspace.h>
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#include <asm/jzsoc.h>
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/*
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* A note on resource allocation:
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*
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* All drivers needing DMA channels, should allocate and release them
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* through the public routines `jz_request_dma()' and `jz_free_dma()'.
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*
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* In order to avoid problems, all processes should allocate resources in
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* the same sequence and release them in the reverse order.
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*
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* So, when allocating DMAs and IRQs, first allocate the DMA, then the IRQ.
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* When releasing them, first release the IRQ, then release the DMA. The
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* main reason for this order is that, if you are requesting the DMA buffer
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* done interrupt, you won't know the irq number until the DMA channel is
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* returned from jz_request_dma().
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*/
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struct jz_dma_chan jz_dma_table[MAX_DMA_NUM] = {
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{dev_id:DMA_ID_BCH_ENC,}, /* DMAC0 channel 0, reserved for BCH */
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{dev_id:-1,}, /* DMAC0 channel 1 */
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{dev_id:-1,}, /* DMAC0 channel 2 */
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{dev_id:-1,}, /* DMAC0 channel 3 */
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{dev_id:-1,}, /* DMAC1 channel 0 */
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{dev_id:-1,}, /* DMAC1 channel 1 */
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{dev_id:-1,}, /* DMAC1 channel 2 */
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{dev_id:-1,}, /* DMAC1 channel 3 */
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};
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// Device FIFO addresses and default DMA modes
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static const struct {
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unsigned int fifo_addr;
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unsigned int dma_mode;
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unsigned int dma_source;
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} dma_dev_table[DMA_ID_MAX] = {
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{0, DMA_AUTOINIT, DMAC_DRSR_RS_EXT}, /* External request with DREQn */
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{0x18000000, DMA_AUTOINIT, DMAC_DRSR_RS_NAND}, /* NAND request */
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{CPHYSADDR(BCH_DR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_BCH_ENC},
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{CPHYSADDR(BCH_DR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_BCH_DEC},
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{0, DMA_AUTOINIT, DMAC_DRSR_RS_AUTO},
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// {CPHYSADDR(TSSI_FIFO), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_TSSIIN},
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{CPHYSADDR(UART3_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART3OUT},
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{CPHYSADDR(UART3_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART3IN},
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{CPHYSADDR(UART2_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART2OUT},
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{CPHYSADDR(UART2_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART2IN},
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{CPHYSADDR(UART1_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART1OUT},
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{CPHYSADDR(UART1_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART1IN},
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{CPHYSADDR(UART0_TDR), DMA_8BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_UART0OUT},
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{CPHYSADDR(UART0_RDR), DMA_8BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_UART0IN},
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{CPHYSADDR(SSI_DR(0)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_SSI0OUT},
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{CPHYSADDR(SSI_DR(0)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SSI0IN},
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{CPHYSADDR(AIC_DR), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_AICOUT},
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{CPHYSADDR(AIC_DR), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_AICIN},
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{CPHYSADDR(MSC_TXFIFO(0)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_MSC0OUT},
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{CPHYSADDR(MSC_RXFIFO(0)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_MSC0IN},
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{0, DMA_AUTOINIT, DMAC_DRSR_RS_TCU},
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{SADC_TSDAT, DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SADC},/* Touch Screen Data Register */
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{CPHYSADDR(MSC_TXFIFO(1)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_MSC1OUT}, /* SSC1 TX */
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{CPHYSADDR(MSC_RXFIFO(1)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_MSC1IN}, /* SSC1 RX */
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{CPHYSADDR(SSI_DR(1)), DMA_32BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_SSI1OUT},
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{CPHYSADDR(SSI_DR(1)), DMA_32BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_SSI1IN},
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{CPHYSADDR(PCM_DP), DMA_16BIT_TX_CMD | DMA_MODE_WRITE, DMAC_DRSR_RS_PMOUT},
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{CPHYSADDR(PCM_DP), DMA_16BIT_RX_CMD | DMA_MODE_READ, DMAC_DRSR_RS_PMIN},
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{},
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};
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int jz_dma_read_proc(char *buf, char **start, off_t fpos,
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int length, int *eof, void *data)
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{
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int i, len = 0;
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struct jz_dma_chan *chan;
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for (i = 0; i < MAX_DMA_NUM; i++) {
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if ((chan = get_dma_chan(i)) != NULL) {
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len += sprintf(buf + len, "%2d: %s\n",
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i, chan->dev_str);
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}
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}
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if (fpos >= len) {
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*start = buf;
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*eof = 1;
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return 0;
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}
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*start = buf + fpos;
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if ((len -= fpos) > length)
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return length;
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*eof = 1;
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return len;
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}
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void dump_jz_dma_channel(unsigned int dmanr)
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{
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struct jz_dma_chan *chan;
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if (dmanr > MAX_DMA_NUM)
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return;
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chan = &jz_dma_table[dmanr];
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printk("DMA%d Registers:\n", dmanr);
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printk(" DMACR = 0x%08x\n", REG_DMAC_DMACR(chan->io/HALF_DMA_NUM));
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printk(" DSAR = 0x%08x\n", REG_DMAC_DSAR(dmanr));
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printk(" DTAR = 0x%08x\n", REG_DMAC_DTAR(dmanr));
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printk(" DTCR = 0x%08x\n", REG_DMAC_DTCR(dmanr));
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printk(" DRSR = 0x%08x\n", REG_DMAC_DRSR(dmanr));
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printk(" DCCSR = 0x%08x\n", REG_DMAC_DCCSR(dmanr));
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printk(" DCMD = 0x%08x\n", REG_DMAC_DCMD(dmanr));
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printk(" DDA = 0x%08x\n", REG_DMAC_DDA(dmanr));
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printk(" DMADBR = 0x%08x\n", REG_DMAC_DMADBR(chan->io/HALF_DMA_NUM));
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}
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/**
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* jz_request_dma - dynamically allcate an idle DMA channel to return
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* @dev_id: the specified dma device id or DMA_ID_RAW_SET
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* @dev_str: the specified dma device string name
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* @irqhandler: the irq handler, or NULL
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* @irqflags: the irq handler flags
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* @irq_dev_id: the irq handler device id for shared irq
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*
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* Finds a free channel, and binds the requested device to it.
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* Returns the allocated channel number, or negative on error.
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* Requests the DMA done IRQ if irqhandler != NULL.
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*
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*/
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/*int jz_request_dma(int dev_id, const char *dev_str,
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void (*irqhandler)(int, void *, struct pt_regs *),
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unsigned long irqflags,
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void *irq_dev_id)
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*/
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int jz_request_dma(int dev_id, const char *dev_str,
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irqreturn_t (*irqhandler)(int, void *),
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unsigned long irqflags,
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void *irq_dev_id)
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{
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struct jz_dma_chan *chan;
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int i, ret;
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if (dev_id < 0 || dev_id >= DMA_ID_MAX)
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return -EINVAL;
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for (i = 0; i < MAX_DMA_NUM; i++) {
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if (jz_dma_table[i].dev_id < 0)
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break;
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}
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if (i == MAX_DMA_NUM) /* no free channel */
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return -ENODEV;
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/* we got a free channel */
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chan = &jz_dma_table[i];
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if (irqhandler) {
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chan->irq = IRQ_DMA_0 + i; // allocate irq number
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chan->irq_dev = irq_dev_id;
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if ((ret = request_irq(chan->irq, irqhandler, irqflags,
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dev_str, chan->irq_dev))) {
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chan->irq = -1;
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chan->irq_dev = NULL;
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return ret;
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}
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} else {
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chan->irq = -1;
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chan->irq_dev = NULL;
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}
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// fill it in
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chan->io = i;
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chan->dev_id = dev_id;
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chan->dev_str = dev_str;
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chan->fifo_addr = dma_dev_table[dev_id].fifo_addr;
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chan->mode = dma_dev_table[dev_id].dma_mode;
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chan->source = dma_dev_table[dev_id].dma_source;
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if (i < HALF_DMA_NUM)
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REG_DMAC_DMACKE(0) = 1 << i;
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else
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REG_DMAC_DMACKE(1) = 1 << (i - HALF_DMA_NUM);
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return i;
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}
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void jz_free_dma(unsigned int dmanr)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan) {
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printk("Trying to free DMA%d\n", dmanr);
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return;
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}
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disable_dma(dmanr);
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if (chan->irq)
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free_irq(chan->irq, chan->irq_dev);
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chan->irq = -1;
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chan->irq_dev = NULL;
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chan->dev_id = -1;
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}
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void jz_set_dma_dest_width(int dmanr, int nbit)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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chan->mode &= ~DMAC_DCMD_DWDH_MASK;
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switch (nbit) {
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case 8:
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chan->mode |= DMAC_DCMD_DWDH_8;
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break;
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case 16:
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chan->mode |= DMAC_DCMD_DWDH_16;
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break;
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case 32:
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chan->mode |= DMAC_DCMD_DWDH_32;
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break;
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}
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}
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void jz_set_dma_src_width(int dmanr, int nbit)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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chan->mode &= ~DMAC_DCMD_SWDH_MASK;
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switch (nbit) {
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case 8:
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chan->mode |= DMAC_DCMD_SWDH_8;
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break;
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case 16:
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chan->mode |= DMAC_DCMD_SWDH_16;
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break;
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case 32:
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chan->mode |= DMAC_DCMD_SWDH_32;
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break;
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}
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}
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void jz_set_dma_block_size(int dmanr, int nbyte)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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chan->mode &= ~DMAC_DCMD_DS_MASK;
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switch (nbyte) {
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case 1:
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chan->mode |= DMAC_DCMD_DS_8BIT;
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break;
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case 2:
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chan->mode |= DMAC_DCMD_DS_16BIT;
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break;
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case 4:
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chan->mode |= DMAC_DCMD_DS_32BIT;
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break;
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case 16:
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chan->mode |= DMAC_DCMD_DS_16BYTE;
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break;
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case 32:
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chan->mode |= DMAC_DCMD_DS_32BYTE;
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break;
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}
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}
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unsigned int jz_get_dma_command(int dmanr)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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return chan->mode;
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}
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/**
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* jz_set_dma_mode - do the raw settings for the specified DMA channel
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* @dmanr: the specified DMA channel
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* @mode: dma operate mode, DMA_MODE_READ or DMA_MODE_WRITE
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* @dma_mode: dma raw mode
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* @dma_source: dma raw request source
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* @fifo_addr: dma raw device fifo address
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*
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* Ensure call jz_request_dma(DMA_ID_RAW_SET, ...) first, then call
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* jz_set_dma_mode() rather than set_dma_mode() if you work with
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* and external request dma device.
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*
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* NOTE: Don not dynamically allocate dma channel if one external request
|
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* dma device will occupy this channel.
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*/
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int jz_set_dma_mode(unsigned int dmanr, unsigned int mode,
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unsigned int dma_mode, unsigned int dma_source,
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unsigned int fifo_addr)
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{
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int dev_id, i;
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struct jz_dma_chan *chan;
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if (dmanr > MAX_DMA_NUM)
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return -ENODEV;
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for (i = 0; i < MAX_DMA_NUM; i++) {
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if (jz_dma_table[i].dev_id < 0)
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break;
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}
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if (i == MAX_DMA_NUM)
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return -ENODEV;
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chan = &jz_dma_table[dmanr];
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dev_id = chan->dev_id;
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if (dev_id > 0) {
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printk(KERN_DEBUG "%s sets the allocated DMA channel %d!\n",
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__FUNCTION__, dmanr);
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return -ENODEV;
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}
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/* clone it from the dynamically allocated. */
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if (i != dmanr) {
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chan->irq = jz_dma_table[i].irq;
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chan->irq_dev = jz_dma_table[i].irq_dev;
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chan->dev_str = jz_dma_table[i].dev_str;
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jz_dma_table[i].irq = 0;
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jz_dma_table[i].irq_dev = NULL;
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jz_dma_table[i].dev_id = -1;
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}
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chan->dev_id = DMA_ID_RAW_SET;
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chan->io = dmanr;
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chan->fifo_addr = fifo_addr;
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chan->mode = dma_mode;
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chan->source = dma_source;
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set_dma_mode(dmanr, dma_mode);
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return dmanr;
|
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}
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||
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void enable_dma(unsigned int dmanr)
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{
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struct jz_dma_chan *chan = get_dma_chan(dmanr);
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|
||
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if (!chan)
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return;
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||
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|
||
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REG_DMAC_DCCSR(dmanr) &= ~(DMAC_DCCSR_HLT | DMAC_DCCSR_TT | DMAC_DCCSR_AR);
|
||
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REG_DMAC_DCCSR(dmanr) |= DMAC_DCCSR_NDES; /* No-descriptor transfer */
|
||
|
__dmac_enable_channel(dmanr);
|
||
|
if (chan->irq)
|
||
|
__dmac_channel_enable_irq(dmanr);
|
||
|
}
|
||
|
|
||
|
#define DMA_DISABLE_POLL 0x10000
|
||
|
|
||
|
void disable_dma(unsigned int dmanr)
|
||
|
{
|
||
|
int i;
|
||
|
struct jz_dma_chan *chan = get_dma_chan(dmanr);
|
||
|
|
||
|
if (!chan)
|
||
|
return;
|
||
|
|
||
|
if (!__dmac_channel_enabled(dmanr))
|
||
|
return;
|
||
|
|
||
|
for (i = 0; i < DMA_DISABLE_POLL; i++)
|
||
|
if (__dmac_channel_transmit_end_detected(dmanr))
|
||
|
break;
|
||
|
#if 0
|
||
|
if (i == DMA_DISABLE_POLL)
|
||
|
printk(KERN_INFO "disable_dma: poll expired!\n");
|
||
|
#endif
|
||
|
|
||
|
__dmac_disable_channel(dmanr);
|
||
|
if (chan->irq)
|
||
|
__dmac_channel_disable_irq(dmanr);
|
||
|
}
|
||
|
|
||
|
/* Note: DMA_MODE_MASK is simulated by sw */
|
||
|
void set_dma_mode(unsigned int dmanr, unsigned int mode)
|
||
|
{
|
||
|
struct jz_dma_chan *chan = get_dma_chan(dmanr);
|
||
|
|
||
|
if (!chan)
|
||
|
return;
|
||
|
|
||
|
chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
|
||
|
mode &= DMA_MODE_MASK;
|
||
|
if (mode == DMA_MODE_READ) {
|
||
|
chan->mode |= DMAC_DCMD_DAI;
|
||
|
chan->mode &= ~DMAC_DCMD_SAI;
|
||
|
} else if (mode == DMA_MODE_WRITE) {
|
||
|
chan->mode |= DMAC_DCMD_SAI;
|
||
|
chan->mode &= ~DMAC_DCMD_DAI;
|
||
|
} else {
|
||
|
printk(KERN_DEBUG "set_dma_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
|
||
|
}
|
||
|
REG_DMAC_DCMD(chan->io) = chan->mode & ~DMA_MODE_MASK;
|
||
|
REG_DMAC_DRSR(chan->io) = chan->source;
|
||
|
}
|
||
|
|
||
|
void set_dma_addr(unsigned int dmanr, unsigned int phyaddr)
|
||
|
{
|
||
|
unsigned int mode;
|
||
|
struct jz_dma_chan *chan = get_dma_chan(dmanr);
|
||
|
|
||
|
if (!chan)
|
||
|
return;
|
||
|
|
||
|
mode = chan->mode & DMA_MODE_MASK;
|
||
|
if (mode == DMA_MODE_READ) {
|
||
|
REG_DMAC_DSAR(chan->io) = chan->fifo_addr;
|
||
|
REG_DMAC_DTAR(chan->io) = phyaddr;
|
||
|
} else if (mode == DMA_MODE_WRITE) {
|
||
|
REG_DMAC_DSAR(chan->io) = phyaddr;
|
||
|
REG_DMAC_DTAR(chan->io) = chan->fifo_addr;
|
||
|
} else
|
||
|
printk(KERN_DEBUG "Driver should call set_dma_mode() ahead set_dma_addr()!\n");
|
||
|
}
|
||
|
|
||
|
void set_dma_count(unsigned int dmanr, unsigned int bytecnt)
|
||
|
{
|
||
|
struct jz_dma_chan *chan = get_dma_chan(dmanr);
|
||
|
int dma_ds[] = {4, 1, 2, 16, 32};
|
||
|
unsigned int ds;
|
||
|
|
||
|
if (!chan)
|
||
|
return;
|
||
|
|
||
|
ds = (chan->mode & DMAC_DCMD_DS_MASK) >> DMAC_DCMD_DS_BIT;
|
||
|
REG_DMAC_DTCR(chan->io) = bytecnt / dma_ds[ds]; // transfer count
|
||
|
}
|
||
|
|
||
|
unsigned int get_dma_residue(unsigned int dmanr)
|
||
|
{
|
||
|
unsigned int count, ds;
|
||
|
int dma_ds[] = {4, 1, 2, 16, 32};
|
||
|
struct jz_dma_chan *chan = get_dma_chan(dmanr);
|
||
|
if (!chan)
|
||
|
return 0;
|
||
|
|
||
|
ds = (chan->mode & DMAC_DCMD_DS_MASK) >> DMAC_DCMD_DS_BIT;
|
||
|
count = REG_DMAC_DTCR(chan->io);
|
||
|
count = count * dma_ds[ds];
|
||
|
|
||
|
return count;
|
||
|
}
|
||
|
|
||
|
void jz_set_oss_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt)
|
||
|
{
|
||
|
struct jz_dma_chan *chan = get_dma_chan(dmanr);
|
||
|
|
||
|
if (!chan)
|
||
|
return;
|
||
|
|
||
|
switch (audio_fmt) {
|
||
|
case AFMT_U8:
|
||
|
/* burst mode : 32BIT */
|
||
|
break;
|
||
|
case AFMT_S16_LE:
|
||
|
/* burst mode : 16BYTE */
|
||
|
if (mode == DMA_MODE_READ) {
|
||
|
chan->mode = DMA_AIC_32_16BYTE_RX_CMD | DMA_MODE_READ;
|
||
|
chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
|
||
|
mode &= DMA_MODE_MASK;
|
||
|
chan->mode |= DMAC_DCMD_DAI;
|
||
|
chan->mode &= ~DMAC_DCMD_SAI;
|
||
|
} else if (mode == DMA_MODE_WRITE) {
|
||
|
chan->mode = DMA_AIC_32_16BYTE_TX_CMD | DMA_MODE_WRITE;
|
||
|
//chan->mode = DMA_AIC_16BYTE_TX_CMD | DMA_MODE_WRITE;
|
||
|
chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
|
||
|
mode &= DMA_MODE_MASK;
|
||
|
chan->mode |= DMAC_DCMD_SAI;
|
||
|
chan->mode &= ~DMAC_DCMD_DAI;
|
||
|
} else
|
||
|
printk("oss_dma_burst_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
|
||
|
|
||
|
REG_DMAC_DCMD(chan->io) = chan->mode & ~DMA_MODE_MASK;
|
||
|
REG_DMAC_DRSR(chan->io) = chan->source;
|
||
|
break;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void jz_set_alsa_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fmt)
|
||
|
{
|
||
|
struct jz_dma_chan *chan = get_dma_chan(dmanr);
|
||
|
|
||
|
if (!chan)
|
||
|
return;
|
||
|
|
||
|
switch (audio_fmt) {
|
||
|
case 8:
|
||
|
/* SNDRV_PCM_FORMAT_S8 burst mode : 32BIT */
|
||
|
break;
|
||
|
case 16:
|
||
|
/* SNDRV_PCM_FORMAT_S16_LE burst mode : 16BYTE */
|
||
|
if (mode == DMA_MODE_READ) {
|
||
|
chan->mode = DMA_AIC_16BYTE_RX_CMD | DMA_MODE_READ;
|
||
|
chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
|
||
|
mode &= DMA_MODE_MASK;
|
||
|
chan->mode |= DMAC_DCMD_DAI;
|
||
|
chan->mode &= ~DMAC_DCMD_SAI;
|
||
|
} else if (mode == DMA_MODE_WRITE) {
|
||
|
chan->mode = DMA_AIC_16BYTE_TX_CMD | DMA_MODE_WRITE;
|
||
|
chan->mode |= mode & ~(DMAC_DCMD_SAI | DMAC_DCMD_DAI);
|
||
|
mode &= DMA_MODE_MASK;
|
||
|
chan->mode |= DMAC_DCMD_SAI;
|
||
|
chan->mode &= ~DMAC_DCMD_DAI;
|
||
|
} else
|
||
|
printk("alsa_dma_burst_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
|
||
|
|
||
|
REG_DMAC_DCMD(chan->io) = chan->mode & ~DMA_MODE_MASK;
|
||
|
REG_DMAC_DRSR(chan->io) = chan->source;
|
||
|
break;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
//#define JZ4750D_DMAC_TEST_ENABLE
|
||
|
#undef JZ4750D_DMAC_TEST_ENABLE
|
||
|
|
||
|
#ifdef JZ4750D_DMAC_TEST_ENABLE
|
||
|
|
||
|
/*
|
||
|
* DMA test: external address <--> external address
|
||
|
*/
|
||
|
#define TEST_DMA_SIZE 16*1024
|
||
|
|
||
|
static jz_dma_desc *dma_desc;
|
||
|
|
||
|
static int dma_chan;
|
||
|
static dma_addr_t dma_desc_phys_addr;
|
||
|
static unsigned int dma_src_addr, dma_src_phys_addr, dma_dst_addr, dma_dst_phys_addr;
|
||
|
|
||
|
static int dma_check_result(void *src, void *dst, int size)
|
||
|
{
|
||
|
unsigned int addr1, addr2, i, err = 0;
|
||
|
|
||
|
addr1 = (unsigned int)src;
|
||
|
addr2 = (unsigned int)dst;
|
||
|
|
||
|
for (i = 0; i < size; i += 4) {
|
||
|
if (*(volatile unsigned int *)addr1 != *(volatile unsigned int *)addr2) {
|
||
|
err++;
|
||
|
printk("wrong data at 0x%08x: src 0x%08x dst 0x%08x\n", addr2, *(volatile unsigned int *)addr1, *(volatile unsigned int *)addr2);
|
||
|
}
|
||
|
addr1 += 4;
|
||
|
addr2 += 4;
|
||
|
}
|
||
|
printk("check DMA result err=%d\n", err);
|
||
|
return err;
|
||
|
}
|
||
|
|
||
|
static irqreturn_t jz4750d_dma_irq(int irq, void *dev_id)
|
||
|
{
|
||
|
printk("jz4750d_dma_irq %d\n", irq);
|
||
|
|
||
|
|
||
|
if (__dmac_channel_transmit_halt_detected(dma_chan)) {
|
||
|
printk("DMA HALT\n");
|
||
|
REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN; /* disable DMA */
|
||
|
__dmac_channel_clear_transmit_halt(dma_chan);
|
||
|
}
|
||
|
|
||
|
if (__dmac_channel_address_error_detected(dma_chan)) {
|
||
|
printk("DMA ADDR ERROR\n");
|
||
|
REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN; /* disable DMA */
|
||
|
REG_DMAC_DSAR(dma_chan) = 0; /* clear source address register */
|
||
|
REG_DMAC_DTAR(dma_chan) = 0; /* clear target address register */
|
||
|
__dmac_channel_clear_address_error(dma_chan);
|
||
|
}
|
||
|
|
||
|
if (__dmac_channel_descriptor_invalid_detected(dma_chan)) {
|
||
|
REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN; /* disable DMA */
|
||
|
printk("DMA DESC INVALID\n");
|
||
|
__dmac_channel_clear_descriptor_invalid(dma_chan);
|
||
|
}
|
||
|
|
||
|
if (__dmac_channel_count_terminated_detected(dma_chan)) {
|
||
|
printk("DMA CT\n");
|
||
|
__dmac_channel_clear_count_terminated(dma_chan);
|
||
|
}
|
||
|
|
||
|
if (__dmac_channel_transmit_end_detected(dma_chan)) {
|
||
|
REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN; /* disable DMA */
|
||
|
printk("DMA TT\n");
|
||
|
__dmac_channel_clear_transmit_end(dma_chan);
|
||
|
dump_jz_dma_channel(dma_chan);
|
||
|
dma_check_result((void *)dma_src_addr, (void *)dma_dst_addr, TEST_DMA_SIZE);
|
||
|
}
|
||
|
|
||
|
return IRQ_HANDLED;
|
||
|
}
|
||
|
|
||
|
void dma_nodesc_test(void)
|
||
|
{
|
||
|
unsigned int addr, i;
|
||
|
|
||
|
printk("dma_nodesc_test\n");
|
||
|
|
||
|
/* Request DMA channel and setup irq handler */
|
||
|
dma_chan = jz_request_dma(DMA_ID_AUTO, "auto", jz4750d_dma_irq,
|
||
|
IRQF_DISABLED, NULL);
|
||
|
if (dma_chan < 0) {
|
||
|
printk("Setup irq failed\n");
|
||
|
return;
|
||
|
}
|
||
|
|
||
|
printk("Requested DMA channel = %d\n", dma_chan);
|
||
|
|
||
|
/* Allocate DMA buffers */
|
||
|
dma_src_addr = __get_free_pages(GFP_KERNEL, 2); /* 16KB */
|
||
|
dma_dst_addr = __get_free_pages(GFP_KERNEL, 2); /* 16KB */
|
||
|
|
||
|
dma_src_phys_addr = CPHYSADDR(dma_src_addr);
|
||
|
dma_dst_phys_addr = CPHYSADDR(dma_dst_addr);
|
||
|
|
||
|
printk("Buffer addresses: 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
||
|
dma_src_addr, dma_src_phys_addr, dma_dst_addr, dma_dst_phys_addr);
|
||
|
|
||
|
/* Prepare data for source buffer */
|
||
|
addr = (unsigned int)dma_src_addr;
|
||
|
for (i = 0; i < TEST_DMA_SIZE; i += 4) {
|
||
|
*(volatile unsigned int *)addr = addr;
|
||
|
addr += 4;
|
||
|
}
|
||
|
dma_cache_wback((unsigned long)dma_src_addr, TEST_DMA_SIZE);
|
||
|
|
||
|
/* Init target buffer */
|
||
|
memset((void *)dma_dst_addr, 0, TEST_DMA_SIZE);
|
||
|
dma_cache_wback((unsigned long)dma_dst_addr, TEST_DMA_SIZE);
|
||
|
|
||
|
/* Init DMA module */
|
||
|
printk("Starting DMA\n");
|
||
|
REG_DMAC_DMACR(dma_chan/HALF_DMA_NUM) = 0;
|
||
|
REG_DMAC_DCCSR(dma_chan) = 0;
|
||
|
REG_DMAC_DRSR(dma_chan) = DMAC_DRSR_RS_AUTO;
|
||
|
REG_DMAC_DSAR(dma_chan) = dma_src_phys_addr;
|
||
|
REG_DMAC_DTAR(dma_chan) = dma_dst_phys_addr;
|
||
|
REG_DMAC_DTCR(dma_chan) = 512;
|
||
|
REG_DMAC_DCMD(dma_chan) = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE | DMAC_DCMD_TIE;
|
||
|
REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_NDES | DMAC_DCCSR_EN;
|
||
|
REG_DMAC_DMACR(dma_chan/HALF_DMA_NUM) = DMAC_DMACR_DMAE; /* global DMA enable bit */
|
||
|
|
||
|
printk("DMA started. IMR=%08x\n", REG_INTC_IMR);
|
||
|
|
||
|
/* wait a long time, ensure transfer end */
|
||
|
printk("wait 3s...\n");
|
||
|
mdelay(3000); /* wait 3s */
|
||
|
|
||
|
REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN; /* disable DMA */
|
||
|
/* free buffers */
|
||
|
printk("free DMA buffers\n");
|
||
|
free_pages(dma_src_addr, 2);
|
||
|
free_pages(dma_dst_addr, 2);
|
||
|
|
||
|
if (dma_desc)
|
||
|
free_pages((unsigned int)dma_desc, 0);
|
||
|
|
||
|
/* free dma */
|
||
|
jz_free_dma(dma_chan);
|
||
|
}
|
||
|
|
||
|
void dma_desc_test(void)
|
||
|
{
|
||
|
unsigned int next, addr, i;
|
||
|
static jz_dma_desc *desc;
|
||
|
|
||
|
printk("dma_desc_test\n");
|
||
|
|
||
|
/* Request DMA channel and setup irq handler */
|
||
|
dma_chan = jz_request_dma(DMA_ID_AUTO, "auto", jz4750d_dma_irq,
|
||
|
IRQF_DISABLED, NULL);
|
||
|
if (dma_chan < 0) {
|
||
|
printk("Setup irq failed\n");
|
||
|
return;
|
||
|
}
|
||
|
|
||
|
printk("Requested DMA channel = %d\n", dma_chan);
|
||
|
|
||
|
/* Allocate DMA buffers */
|
||
|
dma_src_addr = __get_free_pages(GFP_KERNEL, 2); /* 16KB */
|
||
|
dma_dst_addr = __get_free_pages(GFP_KERNEL, 2); /* 16KB */
|
||
|
|
||
|
dma_src_phys_addr = CPHYSADDR(dma_src_addr);
|
||
|
dma_dst_phys_addr = CPHYSADDR(dma_dst_addr);
|
||
|
|
||
|
printk("Buffer addresses: 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
||
|
dma_src_addr, dma_src_phys_addr, dma_dst_addr, dma_dst_phys_addr);
|
||
|
|
||
|
/* Prepare data for source buffer */
|
||
|
addr = (unsigned int)dma_src_addr;
|
||
|
for (i = 0; i < TEST_DMA_SIZE; i += 4) {
|
||
|
*(volatile unsigned int *)addr = addr;
|
||
|
addr += 4;
|
||
|
}
|
||
|
dma_cache_wback((unsigned long)dma_src_addr, TEST_DMA_SIZE);
|
||
|
|
||
|
/* Init target buffer */
|
||
|
memset((void *)dma_dst_addr, 0, TEST_DMA_SIZE);
|
||
|
dma_cache_wback((unsigned long)dma_dst_addr, TEST_DMA_SIZE);
|
||
|
|
||
|
/* Allocate DMA descriptors */
|
||
|
dma_desc = (jz_dma_desc *)__get_free_pages(GFP_KERNEL, 0);
|
||
|
dma_desc_phys_addr = CPHYSADDR((unsigned long)dma_desc);
|
||
|
|
||
|
printk("DMA descriptor address: 0x%08x 0x%08x\n", (u32)dma_desc, dma_desc_phys_addr);
|
||
|
|
||
|
/* Setup DMA descriptors */
|
||
|
desc = dma_desc;
|
||
|
next = (dma_desc_phys_addr + (sizeof(jz_dma_desc))) >> 4;
|
||
|
|
||
|
desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE | DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE | DMAC_DCMD_LINK;
|
||
|
desc->dsadr = dma_src_phys_addr; /* DMA source address */
|
||
|
desc->dtadr = dma_dst_phys_addr; /* DMA target address */
|
||
|
desc->ddadr = (next << 24) + 128; /* size: 128*32 bytes = 4096 bytes */
|
||
|
|
||
|
desc++;
|
||
|
next = (dma_desc_phys_addr + 2*(sizeof(jz_dma_desc))) >> 4;
|
||
|
|
||
|
desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_16BYTE | DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE | DMAC_DCMD_LINK;
|
||
|
desc->dsadr = dma_src_phys_addr + 4096; /* DMA source address */
|
||
|
desc->dtadr = dma_dst_phys_addr + 4096; /* DMA target address */
|
||
|
desc->ddadr = (next << 24) + 256; /* size: 256*16 bytes = 4096 bytes */
|
||
|
|
||
|
desc++;
|
||
|
next = (dma_desc_phys_addr + 3*(sizeof(jz_dma_desc))) >> 4;
|
||
|
|
||
|
desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_16BYTE | DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE | DMAC_DCMD_LINK;
|
||
|
desc->dsadr = dma_src_phys_addr + 8192; /* DMA source address */
|
||
|
desc->dtadr = dma_dst_phys_addr + 8192; /* DMA target address */
|
||
|
desc->ddadr = (next << 24) + 256; /* size: 256*16 bytes = 4096 bytes */
|
||
|
|
||
|
desc++;
|
||
|
next = (dma_desc_phys_addr + 4*(sizeof(jz_dma_desc))) >> 4;
|
||
|
|
||
|
desc->dcmd = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_DES_V | DMAC_DCMD_DES_VM | DMAC_DCMD_DES_VIE | DMAC_DCMD_TIE;
|
||
|
desc->dsadr = dma_src_phys_addr + 12*1024; /* DMA source address */
|
||
|
desc->dtadr = dma_dst_phys_addr + 12*1024; /* DMA target address */
|
||
|
desc->ddadr = (next << 24) + 1024; /* size: 1024*4 bytes = 4096 bytes */
|
||
|
|
||
|
dma_cache_wback((unsigned long)dma_desc, 4*(sizeof(jz_dma_desc)));
|
||
|
|
||
|
/* Setup DMA descriptor address */
|
||
|
REG_DMAC_DDA(dma_chan) = dma_desc_phys_addr;
|
||
|
|
||
|
/* Setup request source */
|
||
|
REG_DMAC_DRSR(dma_chan) = DMAC_DRSR_RS_AUTO;
|
||
|
|
||
|
/* Setup DMA channel control/status register */
|
||
|
REG_DMAC_DCCSR(dma_chan) = DMAC_DCCSR_EN; /* descriptor transfer, clear status, start channel */
|
||
|
|
||
|
/* Enable DMA */
|
||
|
REG_DMAC_DMACR(dma_chan/HALF_DMA_NUM) = DMAC_DMACR_DMAE;
|
||
|
|
||
|
/* DMA doorbell set -- start DMA now ... */
|
||
|
REG_DMAC_DMADBSR(dma_chan/HALF_DMA_NUM) = 1 << dma_chan;
|
||
|
|
||
|
printk("DMA started. IMR=%08x\n", REG_INTC_IMR);
|
||
|
/* wait a long time, ensure transfer end */
|
||
|
printk("wait 3s...\n");
|
||
|
mdelay(3000); /* wait 3s */
|
||
|
|
||
|
REG_DMAC_DCCSR(dma_chan) &= ~DMAC_DCCSR_EN; /* disable DMA */
|
||
|
/* free buffers */
|
||
|
printk("free DMA buffers\n");
|
||
|
free_pages(dma_src_addr, 2);
|
||
|
free_pages(dma_dst_addr, 2);
|
||
|
|
||
|
if (dma_desc)
|
||
|
free_pages((unsigned int)dma_desc, 0);
|
||
|
|
||
|
/* free dma */
|
||
|
jz_free_dma(dma_chan);
|
||
|
}
|
||
|
|
||
|
#endif
|
||
|
|
||
|
//EXPORT_SYMBOL_NOVERS(jz_dma_table);
|
||
|
EXPORT_SYMBOL(jz_dma_table);
|
||
|
EXPORT_SYMBOL(jz_request_dma);
|
||
|
EXPORT_SYMBOL(jz_free_dma);
|
||
|
EXPORT_SYMBOL(jz_set_dma_src_width);
|
||
|
EXPORT_SYMBOL(jz_set_dma_dest_width);
|
||
|
EXPORT_SYMBOL(jz_set_dma_block_size);
|
||
|
EXPORT_SYMBOL(jz_set_dma_mode);
|
||
|
EXPORT_SYMBOL(set_dma_mode);
|
||
|
EXPORT_SYMBOL(jz_set_oss_dma);
|
||
|
EXPORT_SYMBOL(jz_set_alsa_dma);
|
||
|
EXPORT_SYMBOL(set_dma_addr);
|
||
|
EXPORT_SYMBOL(set_dma_count);
|
||
|
EXPORT_SYMBOL(get_dma_residue);
|
||
|
EXPORT_SYMBOL(enable_dma);
|
||
|
EXPORT_SYMBOL(disable_dma);
|
||
|
EXPORT_SYMBOL(dump_jz_dma_channel);
|