mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-23 06:11:59 +03:00
110 lines
2.5 KiB
Diff
110 lines
2.5 KiB
Diff
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--- a/arch/mips/lib/memset.S
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+++ b/arch/mips/lib/memset.S
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@@ -19,6 +19,8 @@
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#define LONG_S_R sdr
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#endif
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+#include "prefetch.h"
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+
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#define EX(insn,reg,addr,handler) \
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9: insn reg, addr; \
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.section __ex_table,"a"; \
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@@ -75,6 +77,8 @@ FEXPORT(__bzero)
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bnez t0, .Lsmall_memset
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andi t0, a0, LONGMASK /* aligned? */
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+ prefetch_store a0, a2, t2, t3, t4
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+
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#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
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beqz t0, 1f
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PTR_SUBU t0, LONGSIZE /* alignment in bytes */
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--- a/arch/mips/include/asm/processor.h
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+++ b/arch/mips/include/asm/processor.h
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@@ -354,7 +354,7 @@ unsigned long get_wchan(struct task_stru
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#define prefetch(x) __builtin_prefetch((x), 0, 1)
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#define ARCH_HAS_PREFETCHW
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-#define prefetchw(x) __builtin_prefetch((x), 1, 1)
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+#define prefetchw(x) do {} while (0)
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#endif
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--- /dev/null
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+++ b/arch/mips/lib/prefetch.h
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@@ -0,0 +1,35 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2012 Felix Fietkau <nbd@openwrt.org>
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+ */
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+
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+.macro prefetch_store dst, size, temp1, temp2, temp3
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+#ifdef CONFIG_CPU_MIPS32
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+ li \temp1, ((1 << CONFIG_MIPS_L1_CACHE_SHIFT) - 1)
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+ nor \temp1, \temp1, \temp1
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+
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+ and \temp2, \size, \temp1
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+ beqz \temp2, 2f
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+ nop
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+
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+ move \temp2, \dst
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+ PTR_ADDIU \temp2, ((1 << CONFIG_MIPS_L1_CACHE_SHIFT) - 1)
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+ and \temp2, \temp2, \temp1
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+
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+ move \temp3, \dst
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+ PTR_ADDU \temp3, \size
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+ and \temp3, \temp3, \temp1
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+
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+1: beq \temp2, \temp3, 2f
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+ nop
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+
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+ pref 30, 0(\temp2)
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+
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+ b 1b
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+ PTR_ADDIU \temp2, (1 << CONFIG_MIPS_L1_CACHE_SHIFT)
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+2:
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+#endif
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+.endm
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--- a/arch/mips/lib/memcpy.S
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+++ b/arch/mips/lib/memcpy.S
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@@ -182,6 +182,8 @@
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.set at=v1
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#endif
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+#include "prefetch.h"
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+
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/*
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* A combined memcpy/__copy_user
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* __copy_user sets len to 0 for success; else to an upper bound of
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@@ -199,6 +201,8 @@ FEXPORT(__copy_user)
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*/
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#define rem t8
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+ prefetch_store a0, a2, t0, t1, t2
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+
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R10KCBARRIER(0(ra))
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/*
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* The "issue break"s below are very approximate.
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--- a/arch/mips/lib/memcpy-inatomic.S
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+++ b/arch/mips/lib/memcpy-inatomic.S
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@@ -182,6 +182,8 @@
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.set at=v1
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#endif
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+#include "prefetch.h"
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+
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/*
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* A combined memcpy/__copy_user
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* __copy_user sets len to 0 for success; else to an upper bound of
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@@ -196,6 +198,8 @@ LEAF(__copy_user_inatomic)
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*/
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#define rem t8
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+ prefetch_store dst, len, t0, t1, t2
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+
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/*
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* The "issue break"s below are very approximate.
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* Issue delays for dcache fills will perturb the schedule, as will
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