mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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180 lines
4.1 KiB
C
180 lines
4.1 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include "pci-bcm63xx.h"
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/*
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* swizzle 32bits data to return only the needed part
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*/
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static int postprocess_read(u32 data, int where, unsigned int size)
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{
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u32 ret;
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ret = 0;
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switch (size) {
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case 1:
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ret = (data >> ((where & 3) << 3)) & 0xff;
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break;
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case 2:
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ret = (data >> ((where & 3) << 3)) & 0xffff;
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break;
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case 4:
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ret = data;
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break;
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}
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return ret;
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}
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static int preprocess_write(u32 orig_data, u32 val, int where,
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unsigned int size)
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{
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u32 ret;
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ret = 0;
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switch (size) {
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case 1:
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ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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break;
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case 2:
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ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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break;
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case 4:
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ret = val;
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break;
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}
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return ret;
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}
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/*
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* setup hardware for a configuration cycle with given parameters
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*/
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static int bcm63xx_setup_cfg_access(int type, unsigned int busn,
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unsigned int devfn, int where)
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{
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unsigned int slot, func, reg;
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u32 val;
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slot = PCI_SLOT(devfn);
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func = PCI_FUNC(devfn);
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reg = where >> 2;
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/* sanity check */
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if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
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return 1;
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if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
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return 1;
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if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
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return 1;
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/* ok, setup config access */
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val = (reg << MPI_L2PCFG_REG_SHIFT);
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val |= (func << MPI_L2PCFG_FUNC_SHIFT);
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val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
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val |= MPI_L2PCFG_CFG_USEREG_MASK;
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val |= MPI_L2PCFG_CFG_SEL_MASK;
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/* type 0 cycle for local bus, type 1 cycle for anything else */
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if (type != 0) {
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/* FIXME: how to specify bus ??? */
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val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
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}
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bcm_mpi_writel(val, MPI_L2PCFG_REG);
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return 0;
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}
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static int bcm63xx_do_cfg_read(int type, unsigned int busn,
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unsigned int devfn, int where, int size,
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u32 *val)
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{
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u32 data;
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/* two phase cycle, first we write address, then read data at
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* another location, caller already has a spinlock so no need
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* to add one here */
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if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
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return PCIBIOS_DEVICE_NOT_FOUND;
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iob();
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data = le32_to_cpu(__raw_readl(pci_iospace_start));
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/* restore IO space normal behaviour */
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bcm_mpi_writel(0, MPI_L2PCFG_REG);
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*val = postprocess_read(data, where, size);
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return PCIBIOS_SUCCESSFUL;
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}
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static int bcm63xx_do_cfg_write(int type, unsigned int busn,
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unsigned int devfn, int where, int size,
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u32 val)
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{
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u32 data;
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/* two phase cycle, first we write address, then write data to
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* another location, caller already has a spinlock so no need
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* to add one here */
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if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
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return PCIBIOS_DEVICE_NOT_FOUND;
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iob();
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data = le32_to_cpu(__raw_readl(pci_iospace_start));
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data = preprocess_write(data, val, where, size);
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__raw_writel(cpu_to_le32(data), pci_iospace_start);
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wmb();
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/* no way to know the access is done, we have to wait */
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udelay(500);
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/* restore IO space normal behaviour */
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bcm_mpi_writel(0, MPI_L2PCFG_REG);
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return PCIBIOS_SUCCESSFUL;
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}
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static int bcm63xx_pci_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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int type;
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type = bus->parent ? 1 : 0;
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if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return bcm63xx_do_cfg_read(type, bus->number, devfn,
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where, size, val);
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}
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static int bcm63xx_pci_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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int type;
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type = bus->parent ? 1 : 0;
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if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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return bcm63xx_do_cfg_write(type, bus->number, devfn,
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where, size, val);
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}
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struct pci_ops bcm63xx_pci_ops = {
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.read = bcm63xx_pci_read,
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.write = bcm63xx_pci_write
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};
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