mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-27 20:58:59 +02:00
59 lines
1.9 KiB
Diff
59 lines
1.9 KiB
Diff
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--- a/arch/mips/Makefile
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+++ b/arch/mips/Makefile
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@@ -162,6 +162,26 @@ ifeq (,$(findstring march=octeon, $(cfla
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cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
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endif
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+#
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+# Ralink SoC common stuff
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+#
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+core-$(CONFIG_MIPS_RALINK) += arch/mips/ralink/common/
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+cflags-$(CONFIG_MIPS_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink
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+
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+#
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+# Ralink RT288x
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+#
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+core-$(CONFIG_RALINK_RT288X) += arch/mips/ralink/rt288x/
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+cflags-$(CONFIG_RALINK_RT288X) += -I$(srctree)//arch/mips/include/asm/mach-ralink/rt288x
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+load-$(CONFIG_RALINK_RT288X) += 0xffffffff88000000
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+
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+#
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+# Ralink RT305x
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+#
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+core-$(CONFIG_RALINK_RT305X) += arch/mips/ralink/rt305x/
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+cflags-$(CONFIG_RALINK_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt305x
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+load-$(CONFIG_RALINK_RT305X) += 0xffffffff80000000
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+
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cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
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cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
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cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,)
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -60,6 +60,9 @@ config AR7
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Support for the Texas Instruments AR7 System-on-a-Chip
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family: TNETD7100, 7200 and 7300.
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+config MIPS_RALINK
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+ bool "Ralink MIPS SoC based boards"
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+
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config BCM47XX
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bool "Broadcom BCM47XX based boards"
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select CEVT_R4K
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@@ -714,6 +717,7 @@ source "arch/mips/jazz/Kconfig"
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source "arch/mips/jz4740/Kconfig"
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source "arch/mips/lasat/Kconfig"
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source "arch/mips/pmc-sierra/Kconfig"
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+source "arch/mips/ralink/Kconfig"
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source "arch/mips/powertv/Kconfig"
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source "arch/mips/sgi-ip27/Kconfig"
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source "arch/mips/sibyte/Kconfig"
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@@ -1073,7 +1077,7 @@ config BOOT_ELF32
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config MIPS_L1_CACHE_SHIFT
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int
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- default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
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+ default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || RALINK_RT288X
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default "6" if MIPS_CPU_SCACHE
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default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
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default "5"
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