mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-23 10:01:59 +03:00
273 lines
8.1 KiB
C
273 lines
8.1 KiB
C
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#include <linux/fb.h>
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#include <asm/io.h>
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#include <asm/msr.h>
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#include "geodefb.h"
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#include "video_gx.h"
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void gx_set_dotpll(struct fb_info *info, struct geoderegs *regs)
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{
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int timeout = 1000;
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u64 rstpll, dotpll;
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rdmsrl(MSR_GLCP_SYS_RSTPLL, rstpll);
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rdmsrl(MSR_GLCP_DOTPLL, dotpll);
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dotpll &= 0x00000000ffffffffull;
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dotpll |= regs->msr.dotpll & 0xffffffff00000000ull;
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dotpll |= MSR_GLCP_DOTPLL_DOTRESET;
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dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;
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wrmsrl(MSR_GLCP_DOTPLL, dotpll);
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rstpll |= (regs->msr.rstpll &
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( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 |
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MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 |
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MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3));
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wrmsrl(MSR_GLCP_SYS_RSTPLL, rstpll);
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dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);
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wrmsrl(MSR_GLCP_DOTPLL, dotpll);
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do {
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rdmsrl(MSR_GLCP_DOTPLL, dotpll);
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} while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
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}
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/* FIXME: Make sure nothing is read to clear */
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void gx_save_regs(struct fb_info *info, struct geoderegs *regs)
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{
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struct geodefb_par *par = info->par;
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int i;
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/* Wait for the BLT engine to stop being busy */
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while(readl(par->gp_regs + 0x44) & 0x05);
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rdmsrl(GX_VP_MSR_PAD_SELECT, regs->msr.padsel);
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rdmsrl(MSR_GLCP_DOTPLL, regs->msr.dotpll);
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rdmsrl(MSR_GLCP_SYS_RSTPLL, regs->msr.rstpll);
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writel(0x4758, par->dc_regs + 0x00);
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memcpy(regs->gp.b, par->gp_regs, GP_REG_SIZE);
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memcpy(regs->dc.b, par->dc_regs, DC_REG_SIZE);
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memcpy(regs->vp.b, par->vid_regs, VP_REG_SIZE);
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memcpy(regs->fp.b, par->vid_regs + 0x400, FP_REG_SIZE);
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/* Save the palettes */
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writel(0, par->dc_regs + 0x70);
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for(i = 0; i < DC_PAL_SIZE; i++)
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regs->pal[i] = readl(par->dc_regs + 0x74);
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writel(0, par->vid_regs + 0x38);
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for(i = 0; i < 0xFF; i++)
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regs->gamma[i] = readl(par->vid_regs + 0x40);
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}
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void gx_restore_regs(struct fb_info *info, struct geoderegs *regs)
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{
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struct geodefb_par *par = info->par;
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u32 val, i;
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/* DOTPLL */
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gx_set_dotpll(info, regs);
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/* GP */
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writel(regs->gp.r.dst_offset, par->gp_regs + 0x00);
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writel(regs->gp.r.src_offset, par->gp_regs + 0x04);
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writel(regs->gp.r.stride, par->gp_regs + 0x08);
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writel(regs->gp.r.wid_height, par->gp_regs + 0x0C);
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writel(regs->gp.r.src_color_fg, par->gp_regs + 0x10);
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writel(regs->gp.r.src_color_bg, par->gp_regs + 0x14);
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writel(regs->gp.r.pat_color_0, par->gp_regs + 0x18);
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writel(regs->gp.r.pat_color_1, par->gp_regs + 0x1C);
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writel(regs->gp.r.pat_color_2, par->gp_regs + 0x20);
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writel(regs->gp.r.pat_color_3, par->gp_regs + 0x24);
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writel(regs->gp.r.pat_color_4, par->gp_regs + 0x28);
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writel(regs->gp.r.pat_color_5, par->gp_regs + 0x2C);
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writel(regs->gp.r.pat_data_0, par->gp_regs + 0x30);
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writel(regs->gp.r.pat_data_1, par->gp_regs + 0x34);
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/* Don't write the raster / vector / blt mode regs */
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/* status register is read only */
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writel(regs->gp.r.hst_src, par->gp_regs + 0x48);
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writel(regs->gp.r.base_offset, par->gp_regs + 0x4c);
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/* DC */
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/* Write the unlock value */
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writel(0x4758, par->dc_regs + 0x00);
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writel(0, par->dc_regs + 0x70);
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for(i = 0; i < DC_PAL_SIZE; i++)
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writel(regs->pal[i], par->dc_regs + 0x74);
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/* Write the gcfg register without the enables */
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writel(regs->dc.r.gcfg & ~0x0F, par->dc_regs + 0x04);
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/* Write the vcfg register without the enables */
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writel(regs->dc.r.dcfg & ~0x19, par->dc_regs + 0x08);
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/* Write the rest of the active registers */
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writel(regs->dc.r.fb_st_offset, par->dc_regs + 0x10);
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writel(regs->dc.r.cb_st_offset, par->dc_regs + 0x14);
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writel(regs->dc.r.curs_st_offset, par->dc_regs + 0x18);
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writel(regs->dc.r.icon_st_offset, par->dc_regs + 0x1C);
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writel(regs->dc.r.vid_y_st_offset, par->dc_regs + 0x20);
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writel(regs->dc.r.vid_u_st_offset, par->dc_regs + 0x24);
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writel(regs->dc.r.vid_v_st_offset, par->dc_regs + 0x28);
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writel(regs->dc.r.line_size, par->dc_regs + 0x30);
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writel(regs->dc.r.gfx_pitch, par->dc_regs + 0x34);
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writel(regs->dc.r.vid_yuv_pitch, par->dc_regs + 0x38);
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writel(regs->dc.r.h_active_timing, par->dc_regs + 0x40);
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writel(regs->dc.r.h_blank_timing, par->dc_regs + 0x44);
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writel(regs->dc.r.h_sync_timing, par->dc_regs + 0x48);
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writel(regs->dc.r.v_active_timing, par->dc_regs + 0x50);
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writel(regs->dc.r.v_blank_timing, par->dc_regs + 0x54);
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writel(regs->dc.r.v_sync_timing, par->dc_regs + 0x58);
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writel(regs->dc.r.dc_cursor_x, par->dc_regs + 0x60);
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writel(regs->dc.r.dc_cursor_y, par->dc_regs + 0x64);
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writel(regs->dc.r.dc_icon_x, par->dc_regs + 0x68);
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/* Don't write the line_cnt or diag registers */
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writel(regs->dc.r.dc_vid_ds_delta, par->dc_regs + 0x80);
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writel(regs->dc.r.gliu0_mem_offset, par->dc_regs + 0x84);
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writel(regs->dc.r.dv_acc, par->dc_regs + 0x8C);
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/* VP */
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/* MSR */
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wrmsrl(GX_VP_MSR_PAD_SELECT, regs->msr.padsel);
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writel(0, par->vid_regs + 0x38);
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for(i = 0; i < 0xFF; i++)
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writel((u32) regs->gamma[i], par->vid_regs + 0x40);
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/* Don't enable video yet */
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writel((u32) regs->vp.r.vcfg & ~0x01, par->vid_regs + 0x00);
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/* Don't enable the CRT yet */
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writel((u32) regs->vp.r.dcfg & ~0x0F, par->vid_regs + 0x08);
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/* Write the rest of the VP registers */
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writel((u32) regs->vp.r.vx, par->vid_regs + 0x10);
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writel((u32) regs->vp.r.vy, par->vid_regs + 0x18);
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writel((u32) regs->vp.r.vs, par->vid_regs + 0x20);
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writel((u32) regs->vp.r.vck, par->vid_regs + 0x28);
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writel((u32) regs->vp.r.vcm, par->vid_regs + 0x30);
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writel((u32) regs->vp.r.misc, par->vid_regs + 0x50);
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writel((u32) regs->vp.r.ccs, par->vid_regs + 0x58);
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writel((u32) regs->vp.r.vdc, par->vid_regs + 0x78);
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writel((u32) regs->vp.r.vco, par->vid_regs + 0x80);
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writel((u32) regs->vp.r.crc, par->vid_regs + 0x88);
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writel((u32) regs->vp.r.vde, par->vid_regs + 0x98);
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writel((u32) regs->vp.r.cck, par->vid_regs + 0xA0);
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writel((u32) regs->vp.r.ccm, par->vid_regs + 0xA8);
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writel((u32) regs->vp.r.cc1, par->vid_regs + 0xB0);
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writel((u32) regs->vp.r.cc2, par->vid_regs + 0xB8);
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writel((u32) regs->vp.r.a1x, par->vid_regs + 0xC0);
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writel((u32) regs->vp.r.a1y, par->vid_regs + 0xC8);
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writel((u32) regs->vp.r.a1c, par->vid_regs + 0xD0);
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writel((u32) regs->vp.r.a1t, par->vid_regs + 0xD8);
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writel((u32) regs->vp.r.a2x, par->vid_regs + 0xE0);
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writel((u32) regs->vp.r.a2y, par->vid_regs + 0xE8);
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writel((u32) regs->vp.r.a2c, par->vid_regs + 0xF0);
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writel((u32) regs->vp.r.a2t, par->vid_regs + 0xF8);
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writel((u32) regs->vp.r.a3x, par->vid_regs + 0x100);
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writel((u32) regs->vp.r.a3y, par->vid_regs + 0x108);
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writel((u32) regs->vp.r.a3c, par->vid_regs + 0x110);
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writel((u32) regs->vp.r.a3t, par->vid_regs + 0x118);
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writel((u32) regs->vp.r.vrr, par->vid_regs + 0x120);
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/* FP registers */
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writel((u32) regs->fp.r.pt1, par->vid_regs + 0x400);
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writel((u32) regs->fp.r.pt2, par->vid_regs + 0x408);
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writel((u32) regs->fp.r.dfc, par->vid_regs + 0x418);
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writel(regs->fp.r.blfsr, par->vid_regs + 0x420);
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writel(regs->fp.r.rlfsr, par->vid_regs + 0x428);
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writel(regs->fp.r.fmi, par->vid_regs + 0x430);
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writel(regs->fp.r.fmd, par->vid_regs + 0x438);
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writel(regs->fp.r.dca, par->vid_regs + 0x448);
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writel(regs->fp.r.dmd, par->vid_regs + 0x450);
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writel(regs->fp.r.crc, par->vid_regs + 0x458);
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writel(regs->fp.r.fbb, par->vid_regs + 0x460);
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/* Final enables */
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val = readl(par->vid_regs + 0x410);
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/* Control the panel */
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if (regs->fp.r.pm & (1 << 24)) {
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if (!(val & 0x09))
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writel(regs->fp.r.pm, par->vid_regs + 0x410);
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}
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else {
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if (!(val & 0x05))
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writel(regs->fp.r.pm, par->vid_regs + 0x410);
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}
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/* Turn everything on */
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writel(regs->dc.r.gcfg, par->dc_regs + 0x04);
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writel((u32) regs->vp.r.vcfg, par->vid_regs + 0x00);
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writel((u32) regs->vp.r.dcfg, par->vid_regs + 0x08);
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writel(regs->dc.r.dcfg, par->dc_regs + 0x08);
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}
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#ifdef DEBUG
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void dump_regs(struct fb_info *info, int mode) {
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struct geodefb_par *par = info->par;
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u32 val;
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int i;
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if (mode == 0) {
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for(i = 0; i < GP_REG_SIZE; i += 4) {
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val = readl(par->gp_regs + i);
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}
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}
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if (mode == 1) {
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writel(0x4758, par->dc_regs + 0x00);
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for(i = 0; i < DC_REG_SIZE; i += 4) {
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val = readl(par->dc_regs + i);
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printk("DC%x: %x\n", i, val);
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}
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}
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if (mode == 2) {
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for(i = 0; i < VP_REG_SIZE; i += 8) {
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val = readl(par->vid_regs + i);
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printk("VP%x: %x\n", i, val);
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}
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}
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if (mode == 3) {
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for(i = 0; i < FP_REG_SIZE; i += 8) {
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val = readl(par->vid_regs + 0x400 + i);
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printk("FP%x: %x\n", i, val);
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}
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}
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}
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#endif
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