mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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846 lines
25 KiB
Diff
846 lines
25 KiB
Diff
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From 47d0e8c2743729b4248585d33b55b6aaeac008d5 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Sun, 8 Jan 2012 16:53:15 +0100
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Subject: [PATCH 25/34] bcma: add PCIe host controller
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Some SoCs have a PCIe host controller to make it possible to attach
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some other devices to it, like an other Wifi card.
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This code was tested with an Netgear WNDR3400 (bcm4716 based), but
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should work with all bcma based SoCs.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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arch/mips/pci/pci-bcm47xx.c | 49 +++-
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drivers/bcma/bcma_private.h | 1 +
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drivers/bcma/driver_pci.c | 38 +--
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drivers/bcma/driver_pci_host.c | 576 +++++++++++++++++++++++++++++++++-
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include/linux/bcma/bcma_driver_pci.h | 34 ++
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include/linux/bcma/bcma_regs.h | 27 ++
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6 files changed, 686 insertions(+), 39 deletions(-)
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--- a/arch/mips/pci/pci-bcm47xx.c
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+++ b/arch/mips/pci/pci-bcm47xx.c
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@@ -25,6 +25,7 @@
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/ssb/ssb.h>
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+#include <linux/bcma/bcma.h>
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#include <bcm47xx.h>
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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@@ -32,15 +33,12 @@ int __init pcibios_map_irq(const struct
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return 0;
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}
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-int pcibios_plat_dev_init(struct pci_dev *dev)
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-{
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#ifdef CONFIG_BCM47XX_SSB
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+static int bcm47xx_pcibios_plat_dev_init_ssb(struct pci_dev *dev)
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+{
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int res;
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u8 slot, pin;
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- if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB)
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- return 0;
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-
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res = ssb_pcibios_plat_dev_init(dev);
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if (res < 0) {
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printk(KERN_ALERT "PCI: Failed to init device %s\n",
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@@ -60,6 +58,47 @@ int pcibios_plat_dev_init(struct pci_dev
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}
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dev->irq = res;
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+ return 0;
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+}
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#endif
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+
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+#ifdef CONFIG_BCM47XX_BCMA
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+static int bcm47xx_pcibios_plat_dev_init_bcma(struct pci_dev *dev)
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+{
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+ int res;
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+
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+ res = bcma_core_pci_plat_dev_init(dev);
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+ if (res < 0) {
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+ printk(KERN_ALERT "PCI: Failed to init device %s\n",
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+ pci_name(dev));
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+ return res;
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+ }
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+
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+ res = bcma_core_pci_pcibios_map_irq(dev);
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+
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+ /* IRQ-0 and IRQ-1 are software interrupts. */
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+ if (res < 2) {
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+ printk(KERN_ALERT "PCI: Failed to map IRQ of device %s\n",
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+ pci_name(dev));
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+ return res;
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+ }
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+
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+ dev->irq = res;
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return 0;
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}
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+#endif
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+
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+int pcibios_plat_dev_init(struct pci_dev *dev)
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+{
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+#ifdef CONFIG_BCM47XX_SSB
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+ if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_SSB)
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+ return bcm47xx_pcibios_plat_dev_init_ssb(dev);
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+ else
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+#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA)
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+ return bcm47xx_pcibios_plat_dev_init_bcma(dev);
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+ else
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+#endif
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+ return 0;
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+}
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--- a/drivers/bcma/bcma_private.h
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+++ b/drivers/bcma/bcma_private.h
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@@ -55,6 +55,7 @@ extern void __exit bcma_host_pci_exit(vo
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#endif /* CONFIG_BCMA_HOST_PCI */
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#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
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+bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
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void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
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#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
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--- a/drivers/bcma/driver_pci.c
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+++ b/drivers/bcma/driver_pci.c
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@@ -2,7 +2,7 @@
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* Broadcom specific AMBA
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* PCI Core
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*
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- * Copyright 2005, Broadcom Corporation
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+ * Copyright 2005, 2011, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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* Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
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*
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@@ -179,47 +179,19 @@ static void __devinit bcma_core_pci_clie
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bcma_pcicore_serdes_workaround(pc);
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}
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-static bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
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-{
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- struct bcma_bus *bus = pc->core->bus;
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- u16 chipid_top;
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-
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- chipid_top = (bus->chipinfo.id & 0xFF00);
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- if (chipid_top != 0x4700 &&
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- chipid_top != 0x5300)
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- return false;
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-
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-#ifdef CONFIG_SSB_DRIVER_PCICORE
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- if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
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- return false;
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-#endif /* CONFIG_SSB_DRIVER_PCICORE */
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-
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-#if 0
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- /* TODO: on BCMA we use address from EROM instead of magic formula */
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- u32 tmp;
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- return !mips_busprobe32(tmp, (bus->mmio +
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- (pc->core->core_index * BCMA_CORE_SIZE)));
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-#endif
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-
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- return true;
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-}
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-
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void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc)
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{
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if (pc->setup_done)
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return;
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- if (bcma_core_pci_is_in_hostmode(pc)) {
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#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
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+ pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
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+ if (pc->hostmode)
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bcma_core_pci_hostmode_init(pc);
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-#else
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- pr_err("Driver compiled without support for hostmode PCI\n");
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#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
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- } else {
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- bcma_core_pci_clientmode_init(pc);
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- }
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- pc->setup_done = true;
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+ if (!pc->hostmode)
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+ bcma_core_pci_clientmode_init(pc);
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}
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int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
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--- a/drivers/bcma/driver_pci_host.c
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+++ b/drivers/bcma/driver_pci_host.c
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@@ -2,13 +2,587 @@
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* Broadcom specific AMBA
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* PCI Core in hostmode
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*
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+ * Copyright 2005 - 2011, Broadcom Corporation
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+ * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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+ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
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+ *
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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+#include <linux/export.h>
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#include <linux/bcma/bcma.h>
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+#include <asm/paccess.h>
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+
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+/* Probe a 32bit value on the bus and catch bus exceptions.
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+ * Returns nonzero on a bus exception.
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+ * This is MIPS specific */
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+#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
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+
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+/* Assume one-hot slot wiring */
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+#define BCMA_PCI_SLOT_MAX 16
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+#define PCI_CONFIG_SPACE_SIZE 256
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+
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+bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
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+{
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+ struct bcma_bus *bus = pc->core->bus;
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+ u16 chipid_top;
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+ u32 tmp;
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+
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+ chipid_top = (bus->chipinfo.id & 0xFF00);
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+ if (chipid_top != 0x4700 &&
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+ chipid_top != 0x5300)
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+ return false;
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+
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+ if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
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+ pr_info("This PCI core is disabled and not working\n");
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+ return false;
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+ }
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+
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+ bcma_core_enable(pc->core, 0);
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+
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+ return !mips_busprobe32(tmp, pc->core->io_addr);
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+}
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+
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+static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
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+{
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+ pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
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+ pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
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+ return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
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+}
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+
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+static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
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+ u32 data)
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+{
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+ pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
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+ pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
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+ pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
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+}
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+
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+static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
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+ unsigned int func, unsigned int off)
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+{
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+ u32 addr = 0;
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+
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+ /* Issue config commands only when the data link is up (atleast
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+ * one external pcie device is present).
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+ */
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+ if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
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+ & BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
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+ goto out;
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+
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+ /* Type 0 transaction */
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+ /* Slide the PCI window to the appropriate slot */
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+ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
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+ /* Calculate the address */
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+ addr = pc->host_controller->host_cfg_addr;
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+ addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
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+ addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
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+ addr |= (off & ~3);
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+
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+out:
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+ return addr;
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+}
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+
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+static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
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+ unsigned int func, unsigned int off,
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+ void *buf, int len)
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+{
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+ int err = -EINVAL;
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+ u32 addr, val;
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+ void __iomem *mmio = 0;
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+
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+ WARN_ON(!pc->hostmode);
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+ if (unlikely(len != 1 && len != 2 && len != 4))
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+ goto out;
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+ if (dev == 0) {
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+ /* we support only two functions on device 0 */
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+ if (func > 1)
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+ return -EINVAL;
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+
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+ /* accesses to config registers with offsets >= 256
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+ * requires indirect access.
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+ */
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+ if (off >= PCI_CONFIG_SPACE_SIZE) {
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+ addr = (func << 12);
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+ addr |= (off & 0x0FFF);
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+ val = bcma_pcie_read_config(pc, addr);
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+ } else {
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+ addr = BCMA_CORE_PCI_PCICFG0;
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+ addr |= (func << 8);
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+ addr |= (off & 0xfc);
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+ val = pcicore_read32(pc, addr);
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+ }
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+ } else {
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+ addr = bcma_get_cfgspace_addr(pc, dev, func, off);
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+ if (unlikely(!addr))
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+ goto out;
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+ err = -ENOMEM;
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+ mmio = ioremap_nocache(addr, len);
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+ if (!mmio)
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+ goto out;
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+
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+ if (mips_busprobe32(val, mmio)) {
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+ val = 0xffffffff;
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+ goto unmap;
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+ }
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+
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+ val = readl(mmio);
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+ }
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+ val >>= (8 * (off & 3));
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+
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+ switch (len) {
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+ case 1:
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+ *((u8 *)buf) = (u8)val;
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+ break;
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+ case 2:
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+ *((u16 *)buf) = (u16)val;
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+ break;
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+ case 4:
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+ *((u32 *)buf) = (u32)val;
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+ break;
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+ }
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+ err = 0;
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+unmap:
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+ if (mmio)
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+ iounmap(mmio);
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+out:
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+ return err;
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+}
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+
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+static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
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+ unsigned int func, unsigned int off,
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+ const void *buf, int len)
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+{
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+ int err = -EINVAL;
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+ u32 addr = 0, val = 0;
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+ void __iomem *mmio = 0;
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+ u16 chipid = pc->core->bus->chipinfo.id;
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+
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+ WARN_ON(!pc->hostmode);
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+ if (unlikely(len != 1 && len != 2 && len != 4))
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+ goto out;
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+ if (dev == 0) {
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+ /* accesses to config registers with offsets >= 256
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+ * requires indirect access.
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+ */
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+ if (off < PCI_CONFIG_SPACE_SIZE) {
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+ addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
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+ addr |= (func << 8);
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+ addr |= (off & 0xfc);
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+ mmio = ioremap_nocache(addr, len);
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+ if (!mmio)
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+ goto out;
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+ }
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+ } else {
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+ addr = bcma_get_cfgspace_addr(pc, dev, func, off);
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+ if (unlikely(!addr))
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+ goto out;
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+ err = -ENOMEM;
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+ mmio = ioremap_nocache(addr, len);
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+ if (!mmio)
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+ goto out;
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+
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+ if (mips_busprobe32(val, mmio)) {
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+ val = 0xffffffff;
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+ goto unmap;
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+ }
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+ }
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+
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+ switch (len) {
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+ case 1:
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+ val = readl(mmio);
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+ val &= ~(0xFF << (8 * (off & 3)));
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+ val |= *((const u8 *)buf) << (8 * (off & 3));
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+ break;
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+ case 2:
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+ val = readl(mmio);
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+ val &= ~(0xFFFF << (8 * (off & 3)));
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+ val |= *((const u16 *)buf) << (8 * (off & 3));
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+ break;
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+ case 4:
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+ val = *((const u32 *)buf);
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+ break;
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+ }
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+ if (dev == 0 && !addr) {
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+ /* accesses to config registers with offsets >= 256
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+ * requires indirect access.
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+ */
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+ addr = (func << 12);
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+ addr |= (off & 0x0FFF);
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+ bcma_pcie_write_config(pc, addr, val);
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+ } else {
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+ writel(val, mmio);
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+
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+ if (chipid == 0x4716 || chipid == 0x4748)
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+ readl(mmio);
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+ }
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+
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+ err = 0;
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+unmap:
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+ if (mmio)
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+ iounmap(mmio);
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+out:
|
||
|
+ return err;
|
||
|
+}
|
||
|
+
|
||
|
+static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
|
||
|
+ unsigned int devfn,
|
||
|
+ int reg, int size, u32 *val)
|
||
|
+{
|
||
|
+ unsigned long flags;
|
||
|
+ int err;
|
||
|
+ struct bcma_drv_pci *pc;
|
||
|
+ struct bcma_drv_pci_host *pc_host;
|
||
|
+
|
||
|
+ pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
|
||
|
+ pc = pc_host->pdev;
|
||
|
+
|
||
|
+ spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
|
||
|
+ err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
|
||
|
+ PCI_FUNC(devfn), reg, val, size);
|
||
|
+ spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
|
||
|
+
|
||
|
+ return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
|
||
|
+}
|
||
|
+
|
||
|
+static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
|
||
|
+ unsigned int devfn,
|
||
|
+ int reg, int size, u32 val)
|
||
|
+{
|
||
|
+ unsigned long flags;
|
||
|
+ int err;
|
||
|
+ struct bcma_drv_pci *pc;
|
||
|
+ struct bcma_drv_pci_host *pc_host;
|
||
|
+
|
||
|
+ pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
|
||
|
+ pc = pc_host->pdev;
|
||
|
+
|
||
|
+ spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
|
||
|
+ err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
|
||
|
+ PCI_FUNC(devfn), reg, &val, size);
|
||
|
+ spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
|
||
|
+
|
||
|
+ return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
|
||
|
+}
|
||
|
+
|
||
|
+/* return cap_offset if requested capability exists in the PCI config space */
|
||
|
+static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc,
|
||
|
+ unsigned int dev,
|
||
|
+ unsigned int func, u8 req_cap_id,
|
||
|
+ unsigned char *buf, u32 *buflen)
|
||
|
+{
|
||
|
+ u8 cap_id;
|
||
|
+ u8 cap_ptr = 0;
|
||
|
+ u32 bufsize;
|
||
|
+ u8 byte_val;
|
||
|
+
|
||
|
+ /* check for Header type 0 */
|
||
|
+ bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
|
||
|
+ sizeof(u8));
|
||
|
+ if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
|
||
|
+ return cap_ptr;
|
||
|
+
|
||
|
+ /* check if the capability pointer field exists */
|
||
|
+ bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
|
||
|
+ sizeof(u8));
|
||
|
+ if (!(byte_val & PCI_STATUS_CAP_LIST))
|
||
|
+ return cap_ptr;
|
||
|
+
|
||
|
+ /* check if the capability pointer is 0x00 */
|
||
|
+ bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
|
||
|
+ sizeof(u8));
|
||
|
+ if (cap_ptr == 0x00)
|
||
|
+ return cap_ptr;
|
||
|
+
|
||
|
+ /* loop thr'u the capability list and see if the requested capabilty
|
||
|
+ * exists */
|
||
|
+ bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
|
||
|
+ while (cap_id != req_cap_id) {
|
||
|
+ bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
|
||
|
+ sizeof(u8));
|
||
|
+ if (cap_ptr == 0x00)
|
||
|
+ return cap_ptr;
|
||
|
+ bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
|
||
|
+ sizeof(u8));
|
||
|
+ }
|
||
|
+
|
||
|
+ /* found the caller requested capability */
|
||
|
+ if ((buf != NULL) && (buflen != NULL)) {
|
||
|
+ u8 cap_data;
|
||
|
+
|
||
|
+ bufsize = *buflen;
|
||
|
+ if (!bufsize)
|
||
|
+ return cap_ptr;
|
||
|
+
|
||
|
+ *buflen = 0;
|
||
|
+
|
||
|
+ /* copy the cpability data excluding cap ID and next ptr */
|
||
|
+ cap_data = cap_ptr + 2;
|
||
|
+ if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE)
|
||
|
+ bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
|
||
|
+ *buflen = bufsize;
|
||
|
+ while (bufsize--) {
|
||
|
+ bcma_extpci_read_config(pc, dev, func, cap_data, buf,
|
||
|
+ sizeof(u8));
|
||
|
+ cap_data++;
|
||
|
+ buf++;
|
||
|
+ }
|
||
|
+ }
|
||
|
+
|
||
|
+ return cap_ptr;
|
||
|
+}
|
||
|
+
|
||
|
+/* If the root port is capable of returning Config Request
|
||
|
+ * Retry Status (CRS) Completion Status to software then
|
||
|
+ * enable the feature.
|
||
|
+ */
|
||
|
+static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
|
||
|
+{
|
||
|
+ u8 cap_ptr, root_ctrl, root_cap, dev;
|
||
|
+ u16 val16;
|
||
|
+ int i;
|
||
|
+
|
||
|
+ cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
|
||
|
+ NULL);
|
||
|
+ root_cap = cap_ptr + PCI_EXP_RTCAP;
|
||
|
+ bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
|
||
|
+ if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
|
||
|
+ /* Enable CRS software visibility */
|
||
|
+ root_ctrl = cap_ptr + PCI_EXP_RTCTL;
|
||
|
+ val16 = PCI_EXP_RTCTL_CRSSVE;
|
||
|
+ bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
|
||
|
+ sizeof(u16));
|
||
|
+
|
||
|
+ /* Initiate a configuration request to read the vendor id
|
||
|
+ * field of the device function's config space header after
|
||
|
+ * 100 ms wait time from the end of Reset. If the device is
|
||
|
+ * not done with its internal initialization, it must at
|
||
|
+ * least return a completion TLP, with a completion status
|
||
|
+ * of "Configuration Request Retry Status (CRS)". The root
|
||
|
+ * complex must complete the request to the host by returning
|
||
|
+ * a read-data value of 0001h for the Vendor ID field and
|
||
|
+ * all 1s for any additional bytes included in the request.
|
||
|
+ * Poll using the config reads for max wait time of 1 sec or
|
||
|
+ * until we receive the successful completion status. Repeat
|
||
|
+ * the procedure for all the devices.
|
||
|
+ */
|
||
|
+ for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
|
||
|
+ for (i = 0; i < 100000; i++) {
|
||
|
+ bcma_extpci_read_config(pc, dev, 0,
|
||
|
+ PCI_VENDOR_ID, &val16,
|
||
|
+ sizeof(val16));
|
||
|
+ if (val16 != 0x1)
|
||
|
+ break;
|
||
|
+ udelay(10);
|
||
|
+ }
|
||
|
+ if (val16 == 0x1)
|
||
|
+ pr_err("PCI: Broken device in slot %d\n", dev);
|
||
|
+ }
|
||
|
+ }
|
||
|
+}
|
||
|
|
||
|
void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
|
||
|
{
|
||
|
- pr_err("No support for PCI core in hostmode yet\n");
|
||
|
+ struct bcma_bus *bus = pc->core->bus;
|
||
|
+ struct bcma_drv_pci_host *pc_host;
|
||
|
+ u32 tmp;
|
||
|
+ u32 pci_membase_1G;
|
||
|
+ unsigned long io_map_base;
|
||
|
+
|
||
|
+ pr_info("PCIEcore in host mode found\n");
|
||
|
+
|
||
|
+ pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
|
||
|
+ if (!pc_host) {
|
||
|
+ pr_err("can not allocate memory");
|
||
|
+ return;
|
||
|
+ }
|
||
|
+
|
||
|
+ pc->host_controller = pc_host;
|
||
|
+ pc_host->pci_controller.io_resource = &pc_host->io_resource;
|
||
|
+ pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
|
||
|
+ pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
|
||
|
+ pc_host->pdev = pc;
|
||
|
+
|
||
|
+ pci_membase_1G = BCMA_SOC_PCI_DMA;
|
||
|
+ pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
|
||
|
+
|
||
|
+ pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
|
||
|
+ pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
|
||
|
+
|
||
|
+ pc_host->mem_resource.name = "BCMA PCIcore external memory",
|
||
|
+ pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
|
||
|
+ pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
|
||
|
+ pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
|
||
|
+
|
||
|
+ pc_host->io_resource.name = "BCMA PCIcore external I/O",
|
||
|
+ pc_host->io_resource.start = 0x100;
|
||
|
+ pc_host->io_resource.end = 0x7FF;
|
||
|
+ pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
|
||
|
+
|
||
|
+ /* Reset RC */
|
||
|
+ udelay(3000);
|
||
|
+ pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
|
||
|
+ udelay(1000);
|
||
|
+ pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
|
||
|
+ BCMA_CORE_PCI_CTL_RST_OE);
|
||
|
+
|
||
|
+ /* 64 MB I/O access window. On 4716, use
|
||
|
+ * sbtopcie0 to access the device registers. We
|
||
|
+ * can't use address match 2 (1 GB window) region
|
||
|
+ * as mips can't generate 64-bit address on the
|
||
|
+ * backplane.
|
||
|
+ */
|
||
|
+ if (bus->chipinfo.id == 0x4716 || bus->chipinfo.id == 0x4748) {
|
||
|
+ pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
|
||
|
+ pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
|
||
|
+ BCMA_SOC_PCI_MEM_SZ - 1;
|
||
|
+ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
|
||
|
+ BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
|
||
|
+ } else if (bus->chipinfo.id == 0x5300) {
|
||
|
+ tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
|
||
|
+ tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
|
||
|
+ tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
|
||
|
+ if (pc->core->core_unit == 0) {
|
||
|
+ pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
|
||
|
+ pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
|
||
|
+ BCMA_SOC_PCI_MEM_SZ - 1;
|
||
|
+ pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
|
||
|
+ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
|
||
|
+ tmp | BCMA_SOC_PCI_MEM);
|
||
|
+ } else if (pc->core->core_unit == 1) {
|
||
|
+ pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
|
||
|
+ pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
|
||
|
+ BCMA_SOC_PCI_MEM_SZ - 1;
|
||
|
+ pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
|
||
|
+ pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
|
||
|
+ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
|
||
|
+ tmp | BCMA_SOC_PCI1_MEM);
|
||
|
+ }
|
||
|
+ } else
|
||
|
+ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
|
||
|
+ BCMA_CORE_PCI_SBTOPCI_IO);
|
||
|
+
|
||
|
+ /* 64 MB configuration access window */
|
||
|
+ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
|
||
|
+
|
||
|
+ /* 1 GB memory access window */
|
||
|
+ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
|
||
|
+ BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G);
|
||
|
+
|
||
|
+
|
||
|
+ /* As per PCI Express Base Spec 1.1 we need to wait for
|
||
|
+ * at least 100 ms from the end of a reset (cold/warm/hot)
|
||
|
+ * before issuing configuration requests to PCI Express
|
||
|
+ * devices.
|
||
|
+ */
|
||
|
+ udelay(100000);
|
||
|
+
|
||
|
+ bcma_core_pci_enable_crs(pc);
|
||
|
+
|
||
|
+ /* Enable PCI bridge BAR0 memory & master access */
|
||
|
+ tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
||
|
+ bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
|
||
|
+
|
||
|
+ /* Enable PCI interrupts */
|
||
|
+ pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
|
||
|
+
|
||
|
+ /* Ok, ready to run, register it to the system.
|
||
|
+ * The following needs change, if we want to port hostmode
|
||
|
+ * to non-MIPS platform. */
|
||
|
+ io_map_base = (unsigned long)ioremap_nocache(BCMA_SOC_PCI_MEM,
|
||
|
+ 0x04000000);
|
||
|
+ pc_host->pci_controller.io_map_base = io_map_base;
|
||
|
+ set_io_port_base(pc_host->pci_controller.io_map_base);
|
||
|
+ /* Give some time to the PCI controller to configure itself with the new
|
||
|
+ * values. Not waiting at this point causes crashes of the machine. */
|
||
|
+ mdelay(10);
|
||
|
+ register_pci_controller(&pc_host->pci_controller);
|
||
|
+ return;
|
||
|
+}
|
||
|
+
|
||
|
+/* Early PCI fixup for a device on the PCI-core bridge. */
|
||
|
+static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
|
||
|
+{
|
||
|
+ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
|
||
|
+ /* This is not a device on the PCI-core bridge. */
|
||
|
+ return;
|
||
|
+ }
|
||
|
+ if (PCI_SLOT(dev->devfn) != 0)
|
||
|
+ return;
|
||
|
+
|
||
|
+ pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
|
||
|
+
|
||
|
+ /* Enable PCI bridge bus mastering and memory space */
|
||
|
+ pci_set_master(dev);
|
||
|
+ if (pcibios_enable_device(dev, ~0) < 0) {
|
||
|
+ pr_err("PCI: BCMA bridge enable failed\n");
|
||
|
+ return;
|
||
|
+ }
|
||
|
+
|
||
|
+ /* Enable PCI bridge BAR1 prefetch and burst */
|
||
|
+ pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
|
||
|
+}
|
||
|
+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
|
||
|
+
|
||
|
+/* Early PCI fixup for all PCI-cores to set the correct memory address. */
|
||
|
+static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
|
||
|
+{
|
||
|
+ struct resource *res;
|
||
|
+ int pos;
|
||
|
+
|
||
|
+ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
|
||
|
+ /* This is not a device on the PCI-core bridge. */
|
||
|
+ return;
|
||
|
+ }
|
||
|
+ if (PCI_SLOT(dev->devfn) == 0)
|
||
|
+ return;
|
||
|
+
|
||
|
+ pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
|
||
|
+
|
||
|
+ for (pos = 0; pos < 6; pos++) {
|
||
|
+ res = &dev->resource[pos];
|
||
|
+ if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
|
||
|
+ pci_assign_resource(dev, pos);
|
||
|
+ }
|
||
|
+}
|
||
|
+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
|
||
|
+
|
||
|
+/* This function is called when doing a pci_enable_device().
|
||
|
+ * We must first check if the device is a device on the PCI-core bridge. */
|
||
|
+int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
|
||
|
+{
|
||
|
+ struct bcma_drv_pci_host *pc_host;
|
||
|
+
|
||
|
+ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
|
||
|
+ /* This is not a device on the PCI-core bridge. */
|
||
|
+ return -ENODEV;
|
||
|
+ }
|
||
|
+ pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
|
||
|
+ pci_ops);
|
||
|
+
|
||
|
+ pr_info("PCI: Fixing up device %s\n", pci_name(dev));
|
||
|
+
|
||
|
+ /* Fix up interrupt lines */
|
||
|
+ dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
|
||
|
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
|
||
|
+
|
||
|
+/* PCI device IRQ mapping. */
|
||
|
+int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
|
||
|
+{
|
||
|
+ struct bcma_drv_pci_host *pc_host;
|
||
|
+
|
||
|
+ if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
|
||
|
+ /* This is not a device on the PCI-core bridge. */
|
||
|
+ return -ENODEV;
|
||
|
+ }
|
||
|
+
|
||
|
+ pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
|
||
|
+ pci_ops);
|
||
|
+ return bcma_core_mips_irq(pc_host->pdev->core) + 2;
|
||
|
}
|
||
|
+EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
|
||
|
--- a/include/linux/bcma/bcma_driver_pci.h
|
||
|
+++ b/include/linux/bcma/bcma_driver_pci.h
|
||
|
@@ -160,9 +160,40 @@ struct pci_dev;
|
||
|
/* PCIcore specific boardflags */
|
||
|
#define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
|
||
|
|
||
|
+/* PCIE Config space accessing MACROS */
|
||
|
+#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */
|
||
|
+#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */
|
||
|
+#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */
|
||
|
+#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */
|
||
|
+
|
||
|
+#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */
|
||
|
+#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */
|
||
|
+#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
|
||
|
+#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
|
||
|
+
|
||
|
+/* PCIE Root Capability Register bits (Host mode only) */
|
||
|
+#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
|
||
|
+
|
||
|
+struct bcma_drv_pci;
|
||
|
+
|
||
|
+struct bcma_drv_pci_host {
|
||
|
+ struct bcma_drv_pci *pdev;
|
||
|
+
|
||
|
+ u32 host_cfg_addr;
|
||
|
+ spinlock_t cfgspace_lock;
|
||
|
+
|
||
|
+ struct pci_controller pci_controller;
|
||
|
+ struct pci_ops pci_ops;
|
||
|
+ struct resource mem_resource;
|
||
|
+ struct resource io_resource;
|
||
|
+};
|
||
|
+
|
||
|
struct bcma_drv_pci {
|
||
|
struct bcma_device *core;
|
||
|
u8 setup_done:1;
|
||
|
+ u8 hostmode:1;
|
||
|
+
|
||
|
+ struct bcma_drv_pci_host *host_controller;
|
||
|
};
|
||
|
|
||
|
/* Register access */
|
||
|
@@ -173,4 +204,7 @@ extern void __devinit bcma_core_pci_init
|
||
|
extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
|
||
|
struct bcma_device *core, bool enable);
|
||
|
|
||
|
+extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
|
||
|
+extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
|
||
|
+
|
||
|
#endif /* LINUX_BCMA_DRIVER_PCI_H_ */
|
||
|
--- a/include/linux/bcma/bcma_regs.h
|
||
|
+++ b/include/linux/bcma/bcma_regs.h
|
||
|
@@ -56,4 +56,31 @@
|
||
|
#define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
|
||
|
#define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
|
||
|
|
||
|
+/* SiliconBackplane Address Map.
|
||
|
+ * All regions may not exist on all chips.
|
||
|
+ */
|
||
|
+#define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */
|
||
|
+#define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
|
||
|
+#define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024)
|
||
|
+#define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
|
||
|
+#define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
|
||
|
+#define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */
|
||
|
+
|
||
|
+
|
||
|
+#define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
|
||
|
+#define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */
|
||
|
+#define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
|
||
|
+#define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2
|
||
|
+ * (2 ZettaBytes), low 32 bits
|
||
|
+ */
|
||
|
+#define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2
|
||
|
+ * (2 ZettaBytes), high 32 bits
|
||
|
+ */
|
||
|
+
|
||
|
+#define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */
|
||
|
+#define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */
|
||
|
+#define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2
|
||
|
+ * (2 ZettaBytes), high 32 bits
|
||
|
+ */
|
||
|
+
|
||
|
#endif /* LINUX_BCMA_REGS_H_ */
|