mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-24 07:48:59 +02:00
774 lines
20 KiB
C
774 lines
20 KiB
C
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/*
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* drivers/mmc/host/ubicom32sd.c
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* Ubicom32 Secure Digital Host Controller Interface driver
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*
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* (C) Copyright 2009, Ubicom, Inc.
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*
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* This file is part of the Ubicom32 Linux Kernel Port.
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*
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* The Ubicom32 Linux Kernel Port is free software: you can redistribute
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* it and/or modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, either version 2 of the
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* License, or (at your option) any later version.
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*
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* The Ubicom32 Linux Kernel Port is distributed in the hope that it
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* will be useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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* the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with the Ubicom32 Linux Kernel Port. If not,
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* see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/scatterlist.h>
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#include <linux/leds.h>
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#include <linux/gpio.h>
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#include <linux/mmc/host.h>
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#include <asm/ubicom32sd.h>
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#define DRIVER_NAME "ubicom32sd"
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#define sd_printk(...)
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//#define sd_printk printk
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#define SDTIO_VP_VERSION 3
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#define SDTIO_MAX_SG_BLOCKS 16
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enum sdtio_commands {
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SDTIO_COMMAND_NOP,
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SDTIO_COMMAND_SETUP,
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SDTIO_COMMAND_SETUP_SDIO,
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SDTIO_COMMAND_EXECUTE,
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SDTIO_COMMAND_RESET,
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};
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#define SDTIO_COMMAND_SHIFT 24
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#define SDTIO_COMMAND_FLAG_STOP_RSP_CRC (1 << 10)
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#define SDTIO_COMMAND_FLAG_STOP_RSP_136 (1 << 9)
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#define SDTIO_COMMAND_FLAG_STOP_RSP (1 << 8)
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#define SDTIO_COMMAND_FLAG_STOP_CMD (1 << 7)
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#define SDTIO_COMMAND_FLAG_DATA_STREAM (1 << 6)
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#define SDTIO_COMMAND_FLAG_DATA_RD (1 << 5)
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#define SDTIO_COMMAND_FLAG_DATA_WR (1 << 4)
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#define SDTIO_COMMAND_FLAG_CMD_RSP_CRC (1 << 3)
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#define SDTIO_COMMAND_FLAG_CMD_RSP_136 (1 << 2)
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#define SDTIO_COMMAND_FLAG_CMD_RSP (1 << 1)
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#define SDTIO_COMMAND_FLAG_CMD (1 << 0)
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/*
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* SDTIO_COMMAND_SETUP_SDIO
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*/
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#define SDTIO_COMMAND_FLAG_SDIO_INT_EN (1 << 0)
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/*
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* SDTIO_COMMAND_SETUP
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* clock speed in arg
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*/
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#define SDTIO_COMMAND_FLAG_4BIT (1 << 3)
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#define SDTIO_COMMAND_FLAG_1BIT (1 << 2)
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#define SDTIO_COMMAND_FLAG_SET_CLOCK (1 << 1)
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#define SDTIO_COMMAND_FLAG_SET_WIDTH (1 << 0)
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#define SDTIO_COMMAND_FLAG_CMD_RSP_MASK (SDTIO_COMMAND_FLAG_CMD_RSP | SDTIO_COMMAND_FLAG_CMD_RSP_136)
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#define SDTIO_COMMAND_FLAG_STOP_RSP_MASK (SDTIO_COMMAND_FLAG_STOP_RSP | SDTIO_COMMAND_FLAG_STOP_RSP_136)
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#define SDTIO_COMMAND_FLAG_RSP_MASK (SDTIO_COMMAND_FLAG_CMD_RSP_MASK | SDTIO_COMMAND_FLAG_STOP_RSP_MASK)
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struct sdtio_vp_sg {
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volatile void *addr;
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volatile u32_t len;
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};
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#define SDTIO_VP_INT_STATUS_DONE (1 << 31)
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#define SDTIO_VP_INT_STATUS_SDIO_INT (1 << 10)
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#define SDTIO_VP_INT_STATUS_DATA_CRC_ERR (1 << 9)
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#define SDTIO_VP_INT_STATUS_DATA_PROG_ERR (1 << 8)
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#define SDTIO_VP_INT_STATUS_DATA_TIMEOUT (1 << 7)
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#define SDTIO_VP_INT_STATUS_STOP_RSP_CRC (1 << 6)
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#define SDTIO_VP_INT_STATUS_STOP_RSP_TIMEOUT (1 << 5)
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#define SDTIO_VP_INT_STATUS_CMD_RSP_CRC (1 << 4)
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#define SDTIO_VP_INT_STATUS_CMD_RSP_TIMEOUT (1 << 3)
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#define SDTIO_VP_INT_STATUS_CMD_TIMEOUT (1 << 2)
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#define SDTIO_VP_INT_STATUS_CARD1_INSERT (1 << 1)
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#define SDTIO_VP_INT_STATUS_CARD0_INSERT (1 << 0)
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struct sdtio_vp_regs {
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u32_t version;
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u32_t f_max;
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u32_t f_min;
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volatile u32_t int_status;
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volatile u32_t command;
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volatile u32_t arg;
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volatile u32_t cmd_opcode;
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volatile u32_t cmd_arg;
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volatile u32_t cmd_rsp0;
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volatile u32_t cmd_rsp1;
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volatile u32_t cmd_rsp2;
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volatile u32_t cmd_rsp3;
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volatile u32_t stop_opcode;
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volatile u32_t stop_arg;
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volatile u32_t stop_rsp0;
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volatile u32_t stop_rsp1;
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volatile u32_t stop_rsp2;
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volatile u32_t stop_rsp3;
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volatile u32_t data_timeout_ns;
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volatile u16_t data_blksz;
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volatile u16_t data_blkct;
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volatile u32_t data_bytes_transferred;
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volatile u32_t sg_len;
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struct sdtio_vp_sg sg[SDTIO_MAX_SG_BLOCKS];
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};
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struct ubicom32sd_data {
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const struct ubicom32sd_platform_data *pdata;
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struct mmc_host *mmc;
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/*
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* Lock used to protect the data structure
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spinlock_t lock;
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*/
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int int_en;
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int int_pend;
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/*
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* Receive and transmit interrupts used for communicating
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* with hardware
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*/
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int irq_tx;
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int irq_rx;
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/*
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* Current outstanding mmc request
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*/
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struct mmc_request *mrq;
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/*
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* Hardware registers
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*/
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struct sdtio_vp_regs *regs;
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};
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/*****************************************************************************\
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* *
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* Suspend/resume *
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* *
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\*****************************************************************************/
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#if 0//def CONFIG_PM
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int ubicom32sd_suspend_host(struct ubicom32sd_host *host, pm_message_t state)
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{
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int ret;
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ret = mmc_suspend_host(host->mmc, state);
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if (ret)
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return ret;
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free_irq(host->irq, host);
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return 0;
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}
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EXPORT_SYMBOL_GPL(ubicom32sd_suspend_host);
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int ubicom32sd_resume_host(struct ubicom32sd_host *host)
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{
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int ret;
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if (host->flags & UBICOM32SD_USE_DMA) {
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if (host->ops->enable_dma)
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host->ops->enable_dma(host);
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}
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ret = request_irq(host->irq, ubicom32sd_irq, IRQF_SHARED,
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mmc_hostname(host->mmc), host);
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if (ret)
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return ret;
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ubicom32sd_init(host);
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mmiowb();
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ret = mmc_resume_host(host->mmc);
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if (ret)
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return ret;
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return 0;
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}
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EXPORT_SYMBOL_GPL(ubicom32sd_resume_host);
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#endif /* CONFIG_PM */
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/*
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* ubicom32sd_send_command_sync
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*/
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static void ubicom32sd_send_command_sync(struct ubicom32sd_data *ud, u32_t command, u32_t arg)
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{
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ud->regs->command = command;
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ud->regs->arg = arg;
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ubicom32_set_interrupt(ud->irq_tx);
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while (ud->regs->command) {
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ndelay(100);
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}
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}
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/*
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* ubicom32sd_send_command
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*/
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static void ubicom32sd_send_command(struct ubicom32sd_data *ud, u32_t command, u32_t arg)
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{
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ud->regs->command = command;
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ud->regs->arg = arg;
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ubicom32_set_interrupt(ud->irq_tx);
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}
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/*
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* ubicom32sd_reset
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*/
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static void ubicom32sd_reset(struct ubicom32sd_data *ud)
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{
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ubicom32sd_send_command_sync(ud, SDTIO_COMMAND_RESET << SDTIO_COMMAND_SHIFT, 0);
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ud->regs->int_status = 0;
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}
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/*
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* ubicom32sd_mmc_request
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*/
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static void ubicom32sd_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
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{
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struct ubicom32sd_data *ud = (struct ubicom32sd_data *)mmc_priv(mmc);
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u32_t command = SDTIO_COMMAND_EXECUTE << SDTIO_COMMAND_SHIFT;
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int ret = 0;
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WARN(ud->mrq != NULL, "ud->mrq still set to %p\n", ud->mrq);
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//pr_debug("send cmd %08x arg %08x flags %08x\n", cmd->opcode, cmd->arg, cmd->flags);
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if (mrq->cmd) {
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struct mmc_command *cmd = mrq->cmd;
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sd_printk("%s:\t\t\tsetup cmd %02d arg %08x flags %08x\n", mmc_hostname(mmc), cmd->opcode, cmd->arg, cmd->flags);
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ud->regs->cmd_opcode = cmd->opcode;
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ud->regs->cmd_arg = cmd->arg;
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command |= SDTIO_COMMAND_FLAG_CMD;
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if (cmd->flags & MMC_RSP_PRESENT) {
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command |= SDTIO_COMMAND_FLAG_CMD_RSP;
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}
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if (cmd->flags & MMC_RSP_136) {
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command |= SDTIO_COMMAND_FLAG_CMD_RSP_136;
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}
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if (cmd->flags & MMC_RSP_CRC) {
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command |= SDTIO_COMMAND_FLAG_CMD_RSP_CRC;
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}
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}
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if (mrq->data) {
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struct mmc_data *data = mrq->data;
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struct scatterlist *sg = data->sg;
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int i;
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printk("%s:\t\t\tsetup data blksz %d num %d sglen=%d fl=%08x Tns=%u\n", mmc_hostname(mmc), data->blksz, data->blocks, data->sg_len, data->flags, data->timeout_ns);
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sd_printk("%s:\t\t\tsetup data blksz %d num %d sglen=%d fl=%08x Tns=%u\n",
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mmc_hostname(mmc), data->blksz, data->blocks, data->sg_len,
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data->flags, data->timeout_ns);
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if (data->sg_len > SDTIO_MAX_SG_BLOCKS) {
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ret = -EINVAL;
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data->error = -EINVAL;
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goto fail;
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}
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ud->regs->data_timeout_ns = data->timeout_ns;
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ud->regs->data_blksz = data->blksz;
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ud->regs->data_blkct = data->blocks;
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ud->regs->sg_len = data->sg_len;
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/*
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* Load all of our sg list into the driver sg buffer
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*/
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for (i = 0; i < data->sg_len; i++) {
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sd_printk("%s: sg %d = %p %d\n", mmc_hostname(mmc), i, sg_virt(sg), sg->length);
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ud->regs->sg[i].addr = sg_virt(sg);
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ud->regs->sg[i].len = sg->length;
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if (((u32_t)ud->regs->sg[i].addr & 0x03) || (sg->length & 0x03)) {
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sd_printk("%s: Need aligned buffers\n", mmc_hostname(mmc));
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ret = -EINVAL;
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data->error = -EINVAL;
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goto fail;
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}
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sg++;
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}
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if (data->flags & MMC_DATA_READ) {
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command |= SDTIO_COMMAND_FLAG_DATA_RD;
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} else if (data->flags & MMC_DATA_WRITE) {
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command |= SDTIO_COMMAND_FLAG_DATA_WR;
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} else if (data->flags & MMC_DATA_STREAM) {
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command |= SDTIO_COMMAND_FLAG_DATA_STREAM;
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}
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}
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if (mrq->stop) {
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struct mmc_command *stop = mrq->stop;
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sd_printk("%s: \t\t\tsetup stop %02d arg %08x flags %08x\n", mmc_hostname(mmc), stop->opcode, stop->arg, stop->flags);
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ud->regs->stop_opcode = stop->opcode;
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ud->regs->stop_arg = stop->arg;
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command |= SDTIO_COMMAND_FLAG_STOP_CMD;
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if (stop->flags & MMC_RSP_PRESENT) {
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command |= SDTIO_COMMAND_FLAG_STOP_RSP;
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}
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if (stop->flags & MMC_RSP_136) {
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command |= SDTIO_COMMAND_FLAG_STOP_RSP_136;
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}
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if (stop->flags & MMC_RSP_CRC) {
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command |= SDTIO_COMMAND_FLAG_STOP_RSP_CRC;
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}
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}
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ud->mrq = mrq;
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sd_printk("%s: Sending command %08x\n", mmc_hostname(mmc), command);
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ubicom32sd_send_command(ud, command, 0);
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return;
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fail:
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sd_printk("%s: mmcreq ret = %d\n", mmc_hostname(mmc), ret);
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mrq->cmd->error = ret;
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mmc_request_done(mmc, mrq);
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}
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/*
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* ubicom32sd_mmc_set_ios
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*/
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static void ubicom32sd_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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struct ubicom32sd_data *ud = (struct ubicom32sd_data *)mmc_priv(mmc);
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u32_t command = SDTIO_COMMAND_SETUP << SDTIO_COMMAND_SHIFT;
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u32_t arg = 0;
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sd_printk("%s: ios call bw:%u pm:%u clk:%u\n", mmc_hostname(mmc), 1 << ios->bus_width, ios->power_mode, ios->clock);
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switch (ios->bus_width) {
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case MMC_BUS_WIDTH_1:
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command |= SDTIO_COMMAND_FLAG_SET_WIDTH | SDTIO_COMMAND_FLAG_1BIT;
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break;
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case MMC_BUS_WIDTH_4:
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command |= SDTIO_COMMAND_FLAG_SET_WIDTH | SDTIO_COMMAND_FLAG_4BIT;
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break;
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}
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if (ios->clock) {
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arg = ios->clock;
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command |= SDTIO_COMMAND_FLAG_SET_CLOCK;
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}
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switch (ios->power_mode) {
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/*
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* Turn off the SD bus (power + clock)
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*/
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case MMC_POWER_OFF:
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gpio_set_value(ud->pdata->cards[0].pin_pwr, !ud->pdata->cards[0].pwr_polarity);
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command |= SDTIO_COMMAND_FLAG_SET_CLOCK;
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break;
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/*
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* Turn on the power to the SD bus
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*/
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case MMC_POWER_ON:
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gpio_set_value(ud->pdata->cards[0].pin_pwr, ud->pdata->cards[0].pwr_polarity);
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break;
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/*
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* Turn on the clock to the SD bus
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*/
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case MMC_POWER_UP:
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/*
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* Done above
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*/
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break;
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}
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|
|
||
|
ubicom32sd_send_command_sync(ud, command, arg);
|
||
|
|
||
|
/*
|
||
|
* Let the power settle down
|
||
|
*/
|
||
|
udelay(500);
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* ubicom32sd_mmc_get_cd
|
||
|
*/
|
||
|
static int ubicom32sd_mmc_get_cd(struct mmc_host *mmc)
|
||
|
{
|
||
|
struct ubicom32sd_data *ud = (struct ubicom32sd_data *)mmc_priv(mmc);
|
||
|
sd_printk("%s: get cd %u %u\n", mmc_hostname(mmc), ud->pdata->cards[0].pin_cd, gpio_get_value(ud->pdata->cards[0].pin_cd));
|
||
|
|
||
|
return gpio_get_value(ud->pdata->cards[0].pin_cd) ?
|
||
|
ud->pdata->cards[0].cd_polarity :
|
||
|
!ud->pdata->cards[0].cd_polarity;
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* ubicom32sd_mmc_get_ro
|
||
|
*/
|
||
|
static int ubicom32sd_mmc_get_ro(struct mmc_host *mmc)
|
||
|
{
|
||
|
struct ubicom32sd_data *ud = (struct ubicom32sd_data *)mmc_priv(mmc);
|
||
|
sd_printk("%s: get ro %u %u\n", mmc_hostname(mmc), ud->pdata->cards[0].pin_wp, gpio_get_value(ud->pdata->cards[0].pin_wp));
|
||
|
|
||
|
return gpio_get_value(ud->pdata->cards[0].pin_wp) ?
|
||
|
ud->pdata->cards[0].wp_polarity :
|
||
|
!ud->pdata->cards[0].wp_polarity;
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* ubicom32sd_mmc_enable_sdio_irq
|
||
|
*/
|
||
|
static void ubicom32sd_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
|
||
|
{
|
||
|
struct ubicom32sd_data *ud = (struct ubicom32sd_data *)mmc_priv(mmc);
|
||
|
|
||
|
ud->int_en = enable;
|
||
|
if (enable && ud->int_pend) {
|
||
|
ud->int_pend = 0;
|
||
|
mmc_signal_sdio_irq(mmc);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* ubicom32sd_interrupt
|
||
|
*/
|
||
|
static irqreturn_t ubicom32sd_interrupt(int irq, void *dev)
|
||
|
{
|
||
|
struct mmc_host *mmc = (struct mmc_host *)dev;
|
||
|
struct mmc_request *mrq;
|
||
|
struct ubicom32sd_data *ud;
|
||
|
u32_t int_status;
|
||
|
|
||
|
if (!mmc) {
|
||
|
return IRQ_HANDLED;
|
||
|
}
|
||
|
|
||
|
ud = (struct ubicom32sd_data *)mmc_priv(mmc);
|
||
|
if (!ud) {
|
||
|
return IRQ_HANDLED;
|
||
|
}
|
||
|
|
||
|
int_status = ud->regs->int_status;
|
||
|
ud->regs->int_status &= ~int_status;
|
||
|
|
||
|
if (int_status & SDTIO_VP_INT_STATUS_SDIO_INT) {
|
||
|
if (ud->int_en) {
|
||
|
ud->int_pend = 0;
|
||
|
mmc_signal_sdio_irq(mmc);
|
||
|
} else {
|
||
|
ud->int_pend++;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if (!(int_status & SDTIO_VP_INT_STATUS_DONE)) {
|
||
|
return IRQ_HANDLED;
|
||
|
}
|
||
|
|
||
|
mrq = ud->mrq;
|
||
|
if (!mrq) {
|
||
|
sd_printk("%s: Spurious interrupt", mmc_hostname(mmc));
|
||
|
return IRQ_HANDLED;
|
||
|
}
|
||
|
ud->mrq = NULL;
|
||
|
|
||
|
/*
|
||
|
* SDTIO_VP_INT_DONE
|
||
|
*/
|
||
|
if (mrq->cmd->flags & MMC_RSP_PRESENT) {
|
||
|
struct mmc_command *cmd = mrq->cmd;
|
||
|
cmd->error = 0;
|
||
|
|
||
|
if ((cmd->flags & MMC_RSP_CRC) && (int_status & SDTIO_VP_INT_STATUS_CMD_RSP_CRC)) {
|
||
|
cmd->error = -EILSEQ;
|
||
|
} else if (int_status & SDTIO_VP_INT_STATUS_CMD_RSP_TIMEOUT) {
|
||
|
cmd->error = -ETIMEDOUT;
|
||
|
goto done;
|
||
|
} else if (cmd->flags & MMC_RSP_136) {
|
||
|
cmd->resp[0] = ud->regs->cmd_rsp0;
|
||
|
cmd->resp[1] = ud->regs->cmd_rsp1;
|
||
|
cmd->resp[2] = ud->regs->cmd_rsp2;
|
||
|
cmd->resp[3] = ud->regs->cmd_rsp3;
|
||
|
} else {
|
||
|
cmd->resp[0] = ud->regs->cmd_rsp0;
|
||
|
}
|
||
|
sd_printk("%s:\t\t\tResponse %08x %08x %08x %08x err=%d\n", mmc_hostname(mmc), cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error);
|
||
|
}
|
||
|
|
||
|
if (mrq->data) {
|
||
|
struct mmc_data *data = mrq->data;
|
||
|
|
||
|
if (int_status & SDTIO_VP_INT_STATUS_DATA_TIMEOUT) {
|
||
|
data->error = -ETIMEDOUT;
|
||
|
sd_printk("%s:\t\t\tData Timeout\n", mmc_hostname(mmc));
|
||
|
goto done;
|
||
|
} else if (int_status & SDTIO_VP_INT_STATUS_DATA_CRC_ERR) {
|
||
|
data->error = -EILSEQ;
|
||
|
sd_printk("%s:\t\t\tData CRC\n", mmc_hostname(mmc));
|
||
|
goto done;
|
||
|
} else if (int_status & SDTIO_VP_INT_STATUS_DATA_PROG_ERR) {
|
||
|
data->error = -EILSEQ;
|
||
|
sd_printk("%s:\t\t\tData Program Error\n", mmc_hostname(mmc));
|
||
|
goto done;
|
||
|
} else {
|
||
|
data->error = 0;
|
||
|
data->bytes_xfered = ud->regs->data_bytes_transferred;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if (mrq->stop && (mrq->stop->flags & MMC_RSP_PRESENT)) {
|
||
|
struct mmc_command *stop = mrq->stop;
|
||
|
stop->error = 0;
|
||
|
|
||
|
if ((stop->flags & MMC_RSP_CRC) && (int_status & SDTIO_VP_INT_STATUS_STOP_RSP_CRC)) {
|
||
|
stop->error = -EILSEQ;
|
||
|
} else if (int_status & SDTIO_VP_INT_STATUS_STOP_RSP_TIMEOUT) {
|
||
|
stop->error = -ETIMEDOUT;
|
||
|
goto done;
|
||
|
} else if (stop->flags & MMC_RSP_136) {
|
||
|
stop->resp[0] = ud->regs->stop_rsp0;
|
||
|
stop->resp[1] = ud->regs->stop_rsp1;
|
||
|
stop->resp[2] = ud->regs->stop_rsp2;
|
||
|
stop->resp[3] = ud->regs->stop_rsp3;
|
||
|
} else {
|
||
|
stop->resp[0] = ud->regs->stop_rsp0;
|
||
|
}
|
||
|
sd_printk("%s:\t\t\tStop Response %08x %08x %08x %08x err=%d\n", mmc_hostname(mmc), stop->resp[0], stop->resp[1], stop->resp[2], stop->resp[3], stop->error);
|
||
|
}
|
||
|
|
||
|
done:
|
||
|
mmc_request_done(mmc, mrq);
|
||
|
|
||
|
return IRQ_HANDLED;
|
||
|
}
|
||
|
|
||
|
static struct mmc_host_ops ubicom32sd_ops = {
|
||
|
.request = ubicom32sd_mmc_request,
|
||
|
.set_ios = ubicom32sd_mmc_set_ios,
|
||
|
.get_ro = ubicom32sd_mmc_get_ro,
|
||
|
.get_cd = ubicom32sd_mmc_get_cd,
|
||
|
.enable_sdio_irq = ubicom32sd_mmc_enable_sdio_irq,
|
||
|
};
|
||
|
|
||
|
/*
|
||
|
* ubicom32sd_probe
|
||
|
*/
|
||
|
static int __devinit ubicom32sd_probe(struct platform_device *pdev)
|
||
|
{
|
||
|
struct ubicom32sd_platform_data *pdata = (struct ubicom32sd_platform_data *)pdev->dev.platform_data;
|
||
|
struct mmc_host *mmc;
|
||
|
struct ubicom32sd_data *ud;
|
||
|
struct resource *res_regs;
|
||
|
struct resource *res_irq_tx;
|
||
|
struct resource *res_irq_rx;
|
||
|
int ret;
|
||
|
|
||
|
/*
|
||
|
* Get our resources, regs is the hardware driver base address
|
||
|
* and the tx and rx irqs are used to communicate with the
|
||
|
* hardware driver.
|
||
|
*/
|
||
|
res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||
|
res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||
|
res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
|
||
|
if (!res_regs || !res_irq_tx || !res_irq_rx) {
|
||
|
ret = -EINVAL;
|
||
|
goto fail;
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* Reserve any gpios we need
|
||
|
*/
|
||
|
ret = gpio_request(pdata->cards[0].pin_wp, "sd-wp");
|
||
|
if (ret) {
|
||
|
goto fail;
|
||
|
}
|
||
|
gpio_direction_input(pdata->cards[0].pin_wp);
|
||
|
|
||
|
ret = gpio_request(pdata->cards[0].pin_cd, "sd-cd");
|
||
|
if (ret) {
|
||
|
goto fail_cd;
|
||
|
}
|
||
|
gpio_direction_input(pdata->cards[0].pin_cd);
|
||
|
|
||
|
/*
|
||
|
* HACK: for the dual port controller on port F, we don't support the second port right now
|
||
|
*/
|
||
|
if (pdata->ncards > 1) {
|
||
|
ret = gpio_request(pdata->cards[1].pin_pwr, "sd-pwr");
|
||
|
gpio_direction_output(pdata->cards[1].pin_pwr, !pdata->cards[1].pwr_polarity);
|
||
|
gpio_direction_output(pdata->cards[1].pin_pwr, pdata->cards[1].pwr_polarity);
|
||
|
}
|
||
|
|
||
|
ret = gpio_request(pdata->cards[0].pin_pwr, "sd-pwr");
|
||
|
if (ret) {
|
||
|
goto fail_pwr;
|
||
|
}
|
||
|
gpio_direction_output(pdata->cards[0].pin_pwr, !pdata->cards[0].pwr_polarity);
|
||
|
|
||
|
/*
|
||
|
* Allocate the MMC driver, it includes memory for our data.
|
||
|
*/
|
||
|
mmc = mmc_alloc_host(sizeof(struct ubicom32sd_data), &pdev->dev);
|
||
|
if (!mmc) {
|
||
|
ret = -ENOMEM;
|
||
|
goto fail_mmc;
|
||
|
}
|
||
|
ud = (struct ubicom32sd_data *)mmc_priv(mmc);
|
||
|
ud->mmc = mmc;
|
||
|
ud->pdata = pdata;
|
||
|
ud->regs = (struct sdtio_vp_regs *)res_regs->start;
|
||
|
ud->irq_tx = res_irq_tx->start;
|
||
|
ud->irq_rx = res_irq_rx->start;
|
||
|
platform_set_drvdata(pdev, mmc);
|
||
|
|
||
|
ret = request_irq(ud->irq_rx, ubicom32sd_interrupt, IRQF_DISABLED, mmc_hostname(mmc), mmc);
|
||
|
if (ret) {
|
||
|
goto fail_mmc;
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* Fill in the mmc structure
|
||
|
*/
|
||
|
mmc->ops = &ubicom32sd_ops;
|
||
|
mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ |
|
||
|
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
|
||
|
|
||
|
mmc->f_min = ud->regs->f_min;
|
||
|
mmc->f_max = ud->regs->f_max;
|
||
|
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
|
||
|
|
||
|
/*
|
||
|
* Setup some restrictions on transfers
|
||
|
*
|
||
|
* We allow up to SDTIO_MAX_SG_BLOCKS of data to DMA into, there are
|
||
|
* not really any "max_seg_size", "max_req_size", or "max_blk_count"
|
||
|
* restrictions (must be less than U32_MAX though), pick
|
||
|
* something large?!...
|
||
|
*
|
||
|
* The hardware can do up to 4095 bytes per block, since the spec
|
||
|
* only requires 2048, we'll set it to that and not worry about
|
||
|
* potential weird blk lengths.
|
||
|
*/
|
||
|
mmc->max_hw_segs = SDTIO_MAX_SG_BLOCKS;
|
||
|
mmc->max_phys_segs = SDTIO_MAX_SG_BLOCKS;
|
||
|
mmc->max_seg_size = 1024 * 1024;
|
||
|
mmc->max_req_size = 1024 * 1024;
|
||
|
mmc->max_blk_count = 1024;
|
||
|
|
||
|
mmc->max_blk_size = 2048;
|
||
|
|
||
|
ubicom32sd_reset(ud);
|
||
|
|
||
|
/*
|
||
|
* enable interrupts
|
||
|
*/
|
||
|
ud->int_en = 0;
|
||
|
ubicom32sd_send_command_sync(ud, SDTIO_COMMAND_SETUP_SDIO << SDTIO_COMMAND_SHIFT | SDTIO_COMMAND_FLAG_SDIO_INT_EN, 0);
|
||
|
|
||
|
mmc_add_host(mmc);
|
||
|
|
||
|
printk(KERN_INFO "%s at %p, irq %d/%d\n", mmc_hostname(mmc),
|
||
|
ud->regs, ud->irq_tx, ud->irq_rx);
|
||
|
return 0;
|
||
|
|
||
|
fail_mmc:
|
||
|
gpio_free(pdata->cards[0].pin_pwr);
|
||
|
fail_pwr:
|
||
|
gpio_free(pdata->cards[0].pin_cd);
|
||
|
fail_cd:
|
||
|
gpio_free(pdata->cards[0].pin_wp);
|
||
|
fail:
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* ubicom32sd_remove
|
||
|
*/
|
||
|
static int __devexit ubicom32sd_remove(struct platform_device *pdev)
|
||
|
{
|
||
|
struct mmc_host *mmc = platform_get_drvdata(pdev);
|
||
|
|
||
|
platform_set_drvdata(pdev, NULL);
|
||
|
|
||
|
if (mmc) {
|
||
|
struct ubicom32sd_data *ud = (struct ubicom32sd_data *)mmc_priv(mmc);
|
||
|
|
||
|
gpio_free(ud->pdata->cards[0].pin_pwr);
|
||
|
gpio_free(ud->pdata->cards[0].pin_cd);
|
||
|
gpio_free(ud->pdata->cards[0].pin_wp);
|
||
|
|
||
|
mmc_remove_host(mmc);
|
||
|
mmc_free_host(mmc);
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* Note that our data is allocated as part of the mmc structure
|
||
|
* so we don't need to free it.
|
||
|
*/
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static struct platform_driver ubicom32sd_driver = {
|
||
|
.driver = {
|
||
|
.name = DRIVER_NAME,
|
||
|
.owner = THIS_MODULE,
|
||
|
},
|
||
|
.probe = ubicom32sd_probe,
|
||
|
.remove = __devexit_p(ubicom32sd_remove),
|
||
|
#if 0
|
||
|
.suspend = ubicom32sd_suspend,
|
||
|
.resume = ubicom32sd_resume,
|
||
|
#endif
|
||
|
};
|
||
|
|
||
|
/*
|
||
|
* ubicom32sd_init
|
||
|
*/
|
||
|
static int __init ubicom32sd_init(void)
|
||
|
{
|
||
|
return platform_driver_register(&ubicom32sd_driver);
|
||
|
}
|
||
|
module_init(ubicom32sd_init);
|
||
|
|
||
|
/*
|
||
|
* ubicom32sd_exit
|
||
|
*/
|
||
|
static void __exit ubicom32sd_exit(void)
|
||
|
{
|
||
|
platform_driver_unregister(&ubicom32sd_driver);
|
||
|
}
|
||
|
module_exit(ubicom32sd_exit);
|
||
|
|
||
|
MODULE_AUTHOR("Patrick Tjin");
|
||
|
MODULE_DESCRIPTION("Ubicom32 Secure Digital Host Controller Interface driver");
|
||
|
MODULE_LICENSE("GPL");
|