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git://projects.qi-hardware.com/openwrt-xburst.git
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46 lines
1.9 KiB
C
46 lines
1.9 KiB
C
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/*
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* HND SiliconBackplane MIPS core software interface.
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*
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* Copyright 2006, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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* $Id: hndmips.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
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*/
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#ifndef _hndmips_h_
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#define _hndmips_h_
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extern void sb_mips_init(sb_t *sbh, uint shirq_map_base);
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extern bool sb_mips_setclock(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
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extern void enable_pfc(uint32 mode);
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extern uint32 sb_memc_get_ncdl(sb_t *sbh);
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#if defined(BCMPERFSTATS)
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/* enable counting - exclusive version. Only one set of counters allowed at a time */
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extern void hndmips_perf_instrcount_enable(void);
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extern void hndmips_perf_icachecount_enable(void);
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extern void hndmips_perf_dcachecount_enable(void);
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/* start and stop counting */
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#define hndmips_perf_start01() \
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MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000)
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#define hndmips_perf_stop01() \
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MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000)
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/* retrieve coutners - counters *decrement* */
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#define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0))
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#define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1))
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#define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2))
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/* enable counting - modular version. Each counters can be enabled separately. */
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extern void hndmips_perf_icache_hit_enable(void);
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extern void hndmips_perf_icache_miss_enable(void);
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extern uint32 hndmips_perf_read_instrcount(void);
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extern uint32 hndmips_perf_read_cache_miss(void);
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extern uint32 hndmips_perf_read_cache_hit(void);
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#endif /* defined(BCMINTERNAL) || defined (BCMPERFSTATS) */
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#endif /* _hndmips_h_ */
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