mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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404 lines
18 KiB
C
404 lines
18 KiB
C
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/*
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* linux/drivers/net/jz_eth.h
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*
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* Jz4730/Jz5730 On-Chip ethernet driver.
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*
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* Copyright (C) 2005 - 2007 Ingenic Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __JZ_ETH_H__
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#define __JZ_ETH_H__
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/* DMA control and status registers */
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#define DMA_BMR (ETH_BASE + 0x1000) // Bus mode
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#define DMA_TPD (ETH_BASE + 0x1004) // Transmit poll demand register
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#define DMA_RPD (ETH_BASE + 0x1008) // Receieve poll demand register
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#define DMA_RRBA (ETH_BASE + 0x100C) // Receieve descriptor base address
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#define DMA_TRBA (ETH_BASE + 0x1010) // Transmit descriptor base address
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#define DMA_STS (ETH_BASE + 0x1014) // Status register
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#define DMA_OMR (ETH_BASE + 0x1018) // Command register
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#define DMA_IMR (ETH_BASE + 0x101C)
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#define DMA_MFC (ETH_BASE + 0x1020)
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/* DMA CSR8-CSR19 reserved */
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#define DMA_CTA (ETH_BASE + 0x1050)
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#define DMA_CRA (ETH_BASE + 0x1054)
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/* Mac control and status registers */
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#define MAC_MCR (ETH_BASE + 0x0000)
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#define MAC_MAH (ETH_BASE + 0x0004)
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#define MAC_MAL (ETH_BASE + 0x0008)
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#define MAC_HTH (ETH_BASE + 0x000C)
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#define MAC_HTL (ETH_BASE + 0x0010)
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#define MAC_MIIA (ETH_BASE + 0x0014)
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#define MAC_MIID (ETH_BASE + 0x0018)
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#define MAC_FCR (ETH_BASE + 0x001C)
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#define MAC_VTR1 (ETH_BASE + 0x0020)
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#define MAC_VTR2 (ETH_BASE + 0x0024)
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/*
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* Bus Mode Register (DMA_BMR)
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*/
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#define BMR_PBL 0x00003f00 /* Programmable Burst Length */
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#define BMR_DSL 0x0000007c /* Descriptor Skip Length */
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#define BMR_BAR 0x00000002 /* Bus ARbitration */
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#define BMR_SWR 0x00000001 /* Software Reset */
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#define PBL_0 0x00000000 /* DMA burst length = amount in RX FIFO */
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#define PBL_1 0x00000100 /* 1 longword DMA burst length */
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#define PBL_2 0x00000200 /* 2 longwords DMA burst length */
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#define PBL_4 0x00000400 /* 4 longwords DMA burst length */
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#define PBL_8 0x00000800 /* 8 longwords DMA burst length */
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#define PBL_16 0x00001000 /* 16 longwords DMA burst length */
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#define PBL_32 0x00002000 /* 32 longwords DMA burst length */
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#define DSL_0 0x00000000 /* 0 longword / descriptor */
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#define DSL_1 0x00000004 /* 1 longword / descriptor */
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#define DSL_2 0x00000008 /* 2 longwords / descriptor */
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#define DSL_4 0x00000010 /* 4 longwords / descriptor */
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#define DSL_8 0x00000020 /* 8 longwords / descriptor */
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#define DSL_16 0x00000040 /* 16 longwords / descriptor */
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#define DSL_32 0x00000080 /* 32 longwords / descriptor */
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/*
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* Status Register (DMA_STS)
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*/
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#define STS_BE 0x03800000 /* Bus Error Bits */
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#define STS_TS 0x00700000 /* Transmit Process State */
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#define STS_RS 0x000e0000 /* Receive Process State */
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#define TS_STOP 0x00000000 /* Stopped */
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#define TS_FTD 0x00100000 /* Running Fetch Transmit Descriptor */
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#define TS_WEOT 0x00200000 /* Running Wait for End Of Transmission */
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#define TS_QDAT 0x00300000 /* Running Queue skb data into TX FIFO */
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#define TS_RES 0x00400000 /* Reserved */
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#define TS_SPKT 0x00500000 /* Reserved */
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#define TS_SUSP 0x00600000 /* Suspended */
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#define TS_CLTD 0x00700000 /* Running Close Transmit Descriptor */
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#define RS_STOP 0x00000000 /* Stopped */
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#define RS_FRD 0x00020000 /* Running Fetch Receive Descriptor */
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#define RS_CEOR 0x00040000 /* Running Check for End of Receive Packet */
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#define RS_WFRP 0x00060000 /* Running Wait for Receive Packet */
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#define RS_SUSP 0x00080000 /* Suspended */
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#define RS_CLRD 0x000a0000 /* Running Close Receive Descriptor */
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#define RS_FLUSH 0x000c0000 /* Running Flush RX FIFO */
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#define RS_QRFS 0x000e0000 /* Running Queue RX FIFO into RX Skb */
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/*
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* Operation Mode Register (DMA_OMR)
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*/
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#define OMR_TTM 0x00400000 /* Transmit Threshold Mode */
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#define OMR_SF 0x00200000 /* Store and Forward */
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#define OMR_TR 0x0000c000 /* Threshold Control Bits */
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#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
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#define OMR_OSF 0x00000004 /* Operate on Second Frame */
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#define OMR_SR 0x00000002 /* Start/Stop Receive */
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#define TR_18 0x00000000 /* Threshold set to 18 (32) bytes */
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#define TR_24 0x00004000 /* Threshold set to 24 (64) bytes */
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#define TR_32 0x00008000 /* Threshold set to 32 (128) bytes */
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#define TR_40 0x0000c000 /* Threshold set to 40 (256) bytes */
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/*
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* Missed Frames Counters (DMA_MFC)
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*/
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//#define MFC_CNT1 0xffff0000 /* Missed Frames Counter Bits by application */
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#define MFC_CNT1 0x0ffe0000 /* Missed Frames Counter Bits by application */
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#define MFC_CNT2 0x0000ffff /* Missed Frames Counter Bits by controller */
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/*
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* Mac control Register (MAC_MCR)
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*/
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#define MCR_RA 0x80000000 /* Receive All */
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#define MCR_HBD 0x10000000 /* HeartBeat Disable */
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#define MCR_PS 0x08000000 /* Port Select */
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#define MCR_OWD 0x00800000 /* Receive own Disable */
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#define MCR_OM 0x00600000 /* Operating(loopback) Mode */
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#define MCR_FDX 0x00100000 /* Full Duplex Mode */
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#define MCR_PM 0x00080000 /* Pass All Multicast */
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#define MCR_PR 0x00040000 /* Promiscuous Mode */
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#define MCR_IF 0x00020000 /* Inverse Filtering */
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#define MCR_PB 0x00010000 /* Pass Bad Frames */
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#define MCR_HO 0x00008000 /* Hash Only Filtering Mode */
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#define MCR_HP 0x00002000 /* Hash/Perfect Receive Filtering Mode */
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#define MCR_FC 0x00001000 /* Late Collision control */
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#define MCR_BFD 0x00000800 /* Boardcast frame Disable */
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#define MCR_RED 0x00000400 /* Retry Disable */
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#define MCR_APS 0x00000100 /* Automatic pad stripping */
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#define MCR_BL 0x000000c0 /* Back off Limit */
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#define MCR_DC 0x00000020 /* Deferral check */
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#define MCR_TE 0x00000008 /* Transmitter enable */
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#define MCR_RE 0x00000004 /* Receiver enable */
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#define MCR_MII_10 ( OMR_TTM | MCR_PS)
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#define MCR_MII_100 ( MCR_HBD | MCR_PS)
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/* Flow control Register (MAC_FCR) */
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#define FCR_PT 0xffff0000 /* Pause time */
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#define FCR_PCF 0x00000004 /* Pass control frames */
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#define FCR_FCE 0x00000002 /* Flow control enable */
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#define FCR_FCB 0x00000001 /* Flow control busy */
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/* Constants for the interrupt mask and
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* interrupt status registers. (DMA_SIS and DMA_IMR)
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*/
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#define DMA_INT_NI 0x00010000 // Normal interrupt summary
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#define DMA_INT_AI 0x00008000 // Abnormal interrupt summary
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#define DMA_INT_ER 0x00004000 // Early receive interrupt
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#define DMA_INT_FB 0x00002000 // Fatal bus error
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#define DMA_INT_ET 0x00000400 // Early transmit interrupt
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#define DMA_INT_RW 0x00000200 // Receive watchdog timeout
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#define DMA_INT_RS 0x00000100 // Receive stop
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#define DMA_INT_RU 0x00000080 // Receive buffer unavailble
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#define DMA_INT_RI 0x00000040 // Receive interrupt
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#define DMA_INT_UN 0x00000020 // Underflow
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#define DMA_INT_TJ 0x00000008 // Transmit jabber timeout
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#define DMA_INT_TU 0x00000004 // Transmit buffer unavailble
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#define DMA_INT_TS 0x00000002 // Transmit stop
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#define DMA_INT_TI 0x00000001 // Transmit interrupt
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/*
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* Receive Descriptor Bit Summary
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*/
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#define R_OWN 0x80000000 /* Own Bit */
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#define RD_FF 0x40000000 /* Filtering Fail */
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#define RD_FL 0x3fff0000 /* Frame Length */
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#define RD_ES 0x00008000 /* Error Summary */
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#define RD_DE 0x00004000 /* Descriptor Error */
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#define RD_LE 0x00001000 /* Length Error */
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#define RD_RF 0x00000800 /* Runt Frame */
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#define RD_MF 0x00000400 /* Multicast Frame */
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#define RD_FS 0x00000200 /* First Descriptor */
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#define RD_LS 0x00000100 /* Last Descriptor */
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#define RD_TL 0x00000080 /* Frame Too Long */
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#define RD_CS 0x00000040 /* Collision Seen */
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#define RD_FT 0x00000020 /* Frame Type */
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#define RD_RJ 0x00000010 /* Receive Watchdog timeout*/
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#define RD_RE 0x00000008 /* Report on MII Error */
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#define RD_DB 0x00000004 /* Dribbling Bit */
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#define RD_CE 0x00000002 /* CRC Error */
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#define RD_RER 0x02000000 /* Receive End Of Ring */
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#define RD_RCH 0x01000000 /* Second Address Chained */
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#define RD_RBS2 0x003ff800 /* Buffer 2 Size */
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#define RD_RBS1 0x000007ff /* Buffer 1 Size */
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/*
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* Transmit Descriptor Bit Summary
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*/
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#define T_OWN 0x80000000 /* Own Bit */
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#define TD_ES 0x00008000 /* Frame Aborted (error summary)*/
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#define TD_LO 0x00000800 /* Loss Of Carrier */
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#define TD_NC 0x00000400 /* No Carrier */
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#define TD_LC 0x00000200 /* Late Collision */
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#define TD_EC 0x00000100 /* Excessive Collisions */
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#define TD_HF 0x00000080 /* Heartbeat Fail */
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#define TD_CC 0x0000003c /* Collision Counter */
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#define TD_UF 0x00000002 /* Underflow Error */
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#define TD_DE 0x00000001 /* Deferred */
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#define TD_IC 0x80000000 /* Interrupt On Completion */
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#define TD_LS 0x40000000 /* Last Segment */
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#define TD_FS 0x20000000 /* First Segment */
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#define TD_FT1 0x10000000 /* Filtering Type */
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#define TD_SET 0x08000000 /* Setup Packet */
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#define TD_AC 0x04000000 /* Add CRC Disable */
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#define TD_TER 0x02000000 /* Transmit End Of Ring */
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#define TD_TCH 0x01000000 /* Second Address Chained */
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#define TD_DPD 0x00800000 /* Disabled Padding */
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#define TD_FT0 0x00400000 /* Filtering Type */
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#define TD_TBS2 0x003ff800 /* Buffer 2 Size */
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#define TD_TBS1 0x000007ff /* Buffer 1 Size */
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#define PERFECT_F 0x00000000
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#define HASH_F TD_FT0
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#define INVERSE_F TD_FT1
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#define HASH_O_F (TD_FT1 | TD_F0)
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/*
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* Constant setting
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*/
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#define IMR_DEFAULT ( DMA_INT_TI | DMA_INT_RI | \
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DMA_INT_TS | DMA_INT_RS | \
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DMA_INT_TU | DMA_INT_RU | \
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DMA_INT_FB )
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#define IMR_ENABLE (DMA_INT_NI | DMA_INT_AI)
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#define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
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#define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
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#define HASH_TABLE_LEN 512 /* Bits */
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#define HASH_BITS 0x01ff /* 9 LS bits */
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#define SETUP_FRAME_LEN 192 /* Bytes */
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#define IMPERF_PA_OFFSET 156 /* Bytes */
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/*
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* Address Filtering Modes
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*/
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#define PERFECT 0 /* 16 perfect physical addresses */
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#define HASH_PERF 1 /* 1 perfect, 512 multicast addresses */
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#define PERFECT_REJ 2 /* Reject 16 perfect physical addresses */
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#define ALL_HASH 3 /* Hashes all physical & multicast addrs */
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#define ALL 0 /* Clear out all the setup frame */
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#define PHYS_ADDR_ONLY 1 /* Update the physical address only */
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/* MII register */
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#define MII_BMCR 0x00 /* MII Basic Mode Control Register */
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#define MII_BMSR 0x01 /* MII Basic Mode Status Register */
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#define MII_ID1 0x02 /* PHY Identifier Register 1 */
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#define MII_ID2 0x03 /* PHY Identifier Register 2 */
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#define MII_ANAR 0x04 /* Auto Negotiation Advertisement Register */
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#define MII_ANLPAR 0x05 /* Auto Negotiation Link Partner Ability */
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#define MII_ANER 0x06 /* Auto Negotiation Expansion */
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#define MII_DSCR 0x10 /* Davicom Specified Configration Register */
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#define MII_DSCSR 0x11 /* Davicom Specified Configration/Status Register */
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#define MII_10BTCSR 0x12 /* 10base-T Specified Configration/Status Register */
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#define MII_PREAMBLE 0xffffffff /* MII Management Preamble */
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#define MII_TEST 0xaaaaaaaa /* MII Test Signal */
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#define MII_STRD 0x06 /* Start of Frame+Op Code: use low nibble */
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#define MII_STWR 0x0a /* Start of Frame+Op Code: use low nibble */
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/*
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* MII Management Control Register
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*/
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#define MII_CR_RST 0x8000 /* RESET the PHY chip */
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#define MII_CR_LPBK 0x4000 /* Loopback enable */
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#define MII_CR_SPD 0x2000 /* 0: 10Mb/s; 1: 100Mb/s */
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#define MII_CR_ASSE 0x1000 /* Auto Speed Select Enable */
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#define MII_CR_PD 0x0800 /* Power Down */
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#define MII_CR_ISOL 0x0400 /* Isolate Mode */
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#define MII_CR_RAN 0x0200 /* Restart Auto Negotiation */
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#define MII_CR_FDM 0x0100 /* Full Duplex Mode */
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#define MII_CR_CTE 0x0080 /* Collision Test Enable */
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/*
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* MII Management Status Register
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*/
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#define MII_SR_T4C 0x8000 /* 100BASE-T4 capable */
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#define MII_SR_TXFD 0x4000 /* 100BASE-TX Full Duplex capable */
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#define MII_SR_TXHD 0x2000 /* 100BASE-TX Half Duplex capable */
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#define MII_SR_TFD 0x1000 /* 10BASE-T Full Duplex capable */
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#define MII_SR_THD 0x0800 /* 10BASE-T Half Duplex capable */
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#define MII_SR_ASSC 0x0020 /* Auto Speed Selection Complete*/
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#define MII_SR_RFD 0x0010 /* Remote Fault Detected */
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#define MII_SR_ANC 0x0008 /* Auto Negotiation capable */
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#define MII_SR_LKS 0x0004 /* Link Status */
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#define MII_SR_JABD 0x0002 /* Jabber Detect */
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#define MII_SR_XC 0x0001 /* Extended Capabilities */
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/*
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* MII Management Auto Negotiation Advertisement Register
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*/
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#define MII_ANA_TAF 0x03e0 /* Technology Ability Field */
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#define MII_ANA_T4AM 0x0200 /* T4 Technology Ability Mask */
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#define MII_ANA_TXAM 0x0180 /* TX Technology Ability Mask */
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#define MII_ANA_FDAM 0x0140 /* Full Duplex Technology Ability Mask */
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||
|
|
#define MII_ANA_HDAM 0x02a0 /* Half Duplex Technology Ability Mask */
|
||
|
|
#define MII_ANA_100M 0x0380 /* 100Mb Technology Ability Mask */
|
||
|
|
#define MII_ANA_10M 0x0060 /* 10Mb Technology Ability Mask */
|
||
|
|
#define MII_ANA_CSMA 0x0001 /* CSMA-CD Capable */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* MII Management Auto Negotiation Remote End Register
|
||
|
|
*/
|
||
|
|
#define MII_ANLPA_NP 0x8000 /* Next Page (Enable) */
|
||
|
|
#define MII_ANLPA_ACK 0x4000 /* Remote Acknowledge */
|
||
|
|
#define MII_ANLPA_RF 0x2000 /* Remote Fault */
|
||
|
|
#define MII_ANLPA_TAF 0x03e0 /* Technology Ability Field */
|
||
|
|
#define MII_ANLPA_T4AM 0x0200 /* T4 Technology Ability Mask */
|
||
|
|
#define MII_ANLPA_TXAM 0x0180 /* TX Technology Ability Mask */
|
||
|
|
#define MII_ANLPA_FDAM 0x0140 /* Full Duplex Technology Ability Mask */
|
||
|
|
#define MII_ANLPA_HDAM 0x02a0 /* Half Duplex Technology Ability Mask */
|
||
|
|
#define MII_ANLPA_100M 0x0380 /* 100Mb Technology Ability Mask */
|
||
|
|
#define MII_ANLPA_10M 0x0060 /* 10Mb Technology Ability Mask */
|
||
|
|
#define MII_ANLPA_CSMA 0x0001 /* CSMA-CD Capable */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* MII Management DAVICOM Specified Configuration And Status Register
|
||
|
|
*/
|
||
|
|
#define MII_DSCSR_100FDX 0x8000 /* 100M Full Duplex Operation Mode */
|
||
|
|
#define MII_DSCSR_100HDX 0x4000 /* 100M Half Duplex Operation Mode */
|
||
|
|
#define MII_DSCSR_10FDX 0x2000 /* 10M Full Duplex Operation Mode */
|
||
|
|
#define MII_DSCSR_10HDX 0x1000 /* 10M Half Duplex Operation Mode */
|
||
|
|
#define MII_DSCSR_ANMB 0x000f /* Auto-Negotiation Monitor Bits */
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Used by IOCTL
|
||
|
|
*/
|
||
|
|
#define READ_COMMAND (SIOCDEVPRIVATE+4)
|
||
|
|
#define WRITE_COMMAND (SIOCDEVPRIVATE+5)
|
||
|
|
#define GETDRIVERINFO (SIOCDEVPRIVATE+6)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Device data and structure
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define ETH_TX_TIMEOUT (6*HZ)
|
||
|
|
|
||
|
|
#define RX_BUF_SIZE 1536
|
||
|
|
|
||
|
|
#define NUM_RX_DESCS 32
|
||
|
|
#define NUM_TX_DESCS 16
|
||
|
|
|
||
|
|
static const char *media_types[] = {
|
||
|
|
"10BaseT-HD ", "10BaseT-FD ","100baseTx-HD ",
|
||
|
|
"100baseTx-FD", "100baseT4", 0
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef struct {
|
||
|
|
unsigned int status;
|
||
|
|
unsigned int desc1;
|
||
|
|
unsigned int buf1_addr;
|
||
|
|
unsigned int next_addr;
|
||
|
|
} jz_desc_t;
|
||
|
|
|
||
|
|
struct jz_eth_private {
|
||
|
|
jz_desc_t tx_ring[NUM_TX_DESCS]; /* transmit descriptors */
|
||
|
|
jz_desc_t rx_ring[NUM_RX_DESCS]; /* receive descriptors */
|
||
|
|
dma_addr_t dma_tx_ring; /* bus address of tx ring */
|
||
|
|
dma_addr_t dma_rx_ring; /* bus address of rx ring */
|
||
|
|
dma_addr_t dma_rx_buf; /* DMA address of rx buffer */
|
||
|
|
unsigned int vaddr_rx_buf; /* virtual address of rx buffer */
|
||
|
|
|
||
|
|
unsigned int rx_head; /* first rx descriptor */
|
||
|
|
unsigned int tx_head; /* first tx descriptor */
|
||
|
|
unsigned int tx_tail; /* last unacked transmit packet */
|
||
|
|
unsigned int tx_full; /* transmit buffers are full */
|
||
|
|
struct sk_buff *tx_skb[NUM_TX_DESCS]; /* skbuffs for packets to transmit */
|
||
|
|
|
||
|
|
struct net_device_stats stats;
|
||
|
|
spinlock_t lock;
|
||
|
|
|
||
|
|
int media; /* Media (eg TP), mode (eg 100B)*/
|
||
|
|
int full_duplex; /* Current duplex setting. */
|
||
|
|
int link_state;
|
||
|
|
char phys[32]; /* List of attached PHY devices */
|
||
|
|
char valid_phy; /* Current linked phy-id with MAC */
|
||
|
|
int mii_phy_cnt;
|
||
|
|
int phy_type; /* 1-RTL8309,0-DVCOM */
|
||
|
|
struct ethtool_cmd ecmds[32];
|
||
|
|
u16 advertising; /* NWay media advertisement */
|
||
|
|
|
||
|
|
struct task_struct *thread; /* Link cheak thread */
|
||
|
|
int thread_die;
|
||
|
|
struct completion thr_exited;
|
||
|
|
wait_queue_head_t thr_wait;
|
||
|
|
|
||
|
|
struct pm_dev *pmdev;
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif /* __JZ_ETH_H__ */
|