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ar71xx: add AR933x specific frequency initialization code

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27056 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg 2011-05-31 22:53:29 +00:00
parent 9d012c4aae
commit 046f6d9c97
2 changed files with 76 additions and 0 deletions
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55
target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
View File

@ -283,6 +283,56 @@ static void __init ar724x_detect_sys_frequency(void)
ar71xx_ahb_freq = ar71xx_cpu_freq / div;
}
static void __init ar933x_detect_sys_frequency(void)
{
u32 clock_ctrl;
u32 cpu_config;
u32 freq;
u32 t;
t = ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
if (t & AR933X_BOOTSTRAP_REF_CLK_40)
ar71xx_ref_freq = (40 * 1000 * 1000);
else
ar71xx_ref_freq = (25 * 1000 * 1000);
clock_ctrl = ar71xx_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
ar71xx_cpu_freq = ar71xx_ref_freq;
ar71xx_ahb_freq = ar71xx_ref_freq;
ar71xx_ddr_freq = ar71xx_ref_freq;
} else {
cpu_config = ar71xx_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
freq = ar71xx_ref_freq / t;
t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
AR933X_PLL_CPU_CONFIG_NINT_MASK;
freq *= t;
t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
if (t == 0)
t = 1;
freq >>= t;
t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
ar71xx_cpu_freq = freq / t;
t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
ar71xx_ddr_freq = freq / t;
t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
ar71xx_ahb_freq = freq / t;
}
}
static void __init detect_sys_frequency(void)
{
switch (ar71xx_soc) {
@ -303,6 +353,11 @@ static void __init detect_sys_frequency(void)
ar91xx_detect_sys_frequency();
break;
case AR71XX_SOC_AR9330:
case AR71XX_SOC_AR9331:
ar933x_detect_sys_frequency();
break;
case AR71XX_SOC_AR9341:
case AR71XX_SOC_AR9342:
case AR71XX_SOC_AR9344:

21
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
View File

@ -188,6 +188,24 @@ extern enum ar71xx_soc_type ar71xx_soc;
#define AR91XX_ETH0_PLL_SHIFT 20
#define AR91XX_ETH1_PLL_SHIFT 22
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
#define AR934X_PLL_REG_CPU_CONFIG 0x00
#define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8
@ -579,6 +597,9 @@ void ar71xx_ddr_flush(u32 reg);
#define AR724X_RESET_REG_RESET_MODULE 0x1c
#define AR933X_RESET_REG_BOOTSTRAP 0xac
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_RESET_REG_RESET_MODULE 0x1c
#define AR934X_RESET_REG_BOOTSTRAP 0xb0
/* 0 - 25MHz 1 - 40 MHz */